From ef7aea0f31304e4f6eab755a40f2779b2e080cc5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 15 Feb 2012 18:23:31 +0100 Subject: [PATCH] bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY --- examples/simple_gpio.py | 9 +++++---- migen/bank/csrgen.py | 11 +++++++---- migen/bank/description.py | 11 +++++++---- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/examples/simple_gpio.py b/examples/simple_gpio.py index 019c1195..1a738791 100644 --- a/examples/simple_gpio.py +++ b/examples/simple_gpio.py @@ -1,17 +1,18 @@ from migen.fhdl.structure import * from migen.fhdl import verilog from migen.bank import description, csrgen +from migen.bank.description import READ_ONLY, WRITE_ONLY -ninputs = 4 -noutputs = 31 +ninputs = 32 +noutputs = 32 oreg = description.RegisterField("o", noutputs) -ireg = description.RegisterRaw("i", ninputs) +ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY) # input path gpio_in = Signal(BV(ninputs)) gpio_in_s = Signal(BV(ninputs)) # synchronizer -insync = [gpio_in_s.eq(gpio_in), ireg.w.eq(gpio_in_s)] +insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)] inf = Fragment(sync=insync) bank = csrgen.Bank([oreg, ireg]) diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index 88c43615..c8765089 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -71,9 +71,12 @@ class Bank: for reg in self.description: if isinstance(reg, RegisterFields): for field in reg.fields: - if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE: - comb.append(field.r.eq(field.storage)) - if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE: - sync.append(If(field.we, field.storage.eq(field.w))) + if field.access_bus == READ_ONLY and field.access_dev == WRITE_ONLY: + comb.append(field.storage.eq(field.w)) + else: + if field.access_dev == READ_ONLY or field.access_dev == READ_WRITE: + comb.append(field.r.eq(field.storage)) + if field.access_dev == WRITE_ONLY or field.access_dev == READ_WRITE: + sync.append(If(field.we, field.storage.eq(field.w))) return Fragment(comb, sync) diff --git a/migen/bank/description.py b/migen/bank/description.py index 325738f7..415ed809 100644 --- a/migen/bank/description.py +++ b/migen/bank/description.py @@ -17,11 +17,14 @@ class Field: self.access_bus = access_bus self.access_dev = access_dev self.storage = Signal(BV(self.size), reset=reset) - if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE: - self.r = Signal(BV(self.size)) - if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE: + if self.access_bus == READ_ONLY and self.access_dev == WRITE_ONLY: self.w = Signal(BV(self.size)) - self.we = Signal() + else: + if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE: + self.r = Signal(BV(self.size)) + if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE: + self.w = Signal(BV(self.size)) + self.we = Signal() class RegisterFields: def __init__(self, name, fields): -- 2.30.2