From effc41f14003a86481f383d00a9009135f59156e Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 23 Dec 2018 09:20:02 +0000 Subject: [PATCH] back.rtlil: do not translate empty fragments. The resulting Verilog confuses some frontends. --- nmigen/back/rtlil.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 817f9b2..d4a011c 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -627,6 +627,9 @@ def convert_fragment(builder, fragment, name, top): # name) names. memories = OrderedDict() for subfragment, sub_name in fragment.subfragments: + if not subfragment.ports: + continue + sub_params = OrderedDict() if hasattr(subfragment, "parameters"): for param_name, param_value in subfragment.parameters.items(): -- 2.30.2