From f0063c2e8b2ba6ec5e0147121e5ee2d9ee3ad2a4 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Thu, 20 Jan 2011 20:37:22 -0800
Subject: [PATCH] [sim, pk, xcc, opcodes] great instruction renaming of 2011

---
 riscv/execute.h                          | 315 +++++++++++++----------
 riscv/insns/{amo_add.h => amoadd_d.h}    |   0
 riscv/insns/{amow_add.h => amoadd_w.h}   |   0
 riscv/insns/{amo_and.h => amoand_d.h}    |   0
 riscv/insns/{amow_and.h => amoand_w.h}   |   0
 riscv/insns/{amo_max.h => amomax_d.h}    |   0
 riscv/insns/{amow_max.h => amomax_w.h}   |   0
 riscv/insns/{amo_maxu.h => amomaxu_d.h}  |   0
 riscv/insns/{amow_maxu.h => amomaxu_w.h} |   0
 riscv/insns/{amo_min.h => amomin_d.h}    |   0
 riscv/insns/{amow_min.h => amomin_w.h}   |   0
 riscv/insns/{amo_minu.h => amominu_d.h}  |   0
 riscv/insns/{amow_minu.h => amominu_w.h} |   0
 riscv/insns/{amo_or.h => amoor_d.h}      |   0
 riscv/insns/{amow_or.h => amoor_w.h}     |   0
 riscv/insns/{amo_swap.h => amoswap_d.h}  |   0
 riscv/insns/{amow_swap.h => amoswap_w.h} |   0
 riscv/insns/{add_d.h => fadd_d.h}        |   0
 riscv/insns/{add_s.h => fadd_s.h}        |   0
 riscv/insns/{c_eq_d.h => fc_eq_d.h}      |   0
 riscv/insns/{c_eq_s.h => fc_eq_s.h}      |   0
 riscv/insns/{c_le_d.h => fc_le_d.h}      |   0
 riscv/insns/{c_le_s.h => fc_le_s.h}      |   0
 riscv/insns/{c_lt_d.h => fc_lt_d.h}      |   0
 riscv/insns/{c_lt_s.h => fc_lt_s.h}      |   0
 riscv/insns/{cvt_d_l.h => fcvt_d_l.h}    |   0
 riscv/insns/{cvt_d_s.h => fcvt_d_s.h}    |   0
 riscv/insns/{cvt_d_w.h => fcvt_d_w.h}    |   0
 riscv/insns/{cvt_l_d.h => fcvt_l_d.h}    |   0
 riscv/insns/{cvt_l_s.h => fcvt_l_s.h}    |   0
 riscv/insns/{cvt_s_d.h => fcvt_s_d.h}    |   0
 riscv/insns/{cvt_s_l.h => fcvt_s_l.h}    |   0
 riscv/insns/{cvt_s_w.h => fcvt_s_w.h}    |   0
 riscv/insns/{cvt_w_d.h => fcvt_w_d.h}    |   0
 riscv/insns/{cvt_w_s.h => fcvt_w_s.h}    |   0
 riscv/insns/{cvtu_d_l.h => fcvtu_d_l.h}  |   0
 riscv/insns/{cvtu_d_w.h => fcvtu_d_w.h}  |   0
 riscv/insns/{cvtu_l_d.h => fcvtu_l_d.h}  |   0
 riscv/insns/{cvtu_l_s.h => fcvtu_l_s.h}  |   0
 riscv/insns/{cvtu_s_l.h => fcvtu_s_l.h}  |   0
 riscv/insns/{cvtu_s_w.h => fcvtu_s_w.h}  |   0
 riscv/insns/{cvtu_w_d.h => fcvtu_w_d.h}  |   0
 riscv/insns/{cvtu_w_s.h => fcvtu_w_s.h}  |   0
 riscv/insns/{div_d.h => fdiv_d.h}        |   0
 riscv/insns/{div_s.h => fdiv_s.h}        |   0
 riscv/insns/{madd_d.h => fmadd_d.h}      |   0
 riscv/insns/{madd_s.h => fmadd_s.h}      |   0
 riscv/insns/{msub_d.h => fmsub_d.h}      |   0
 riscv/insns/{msub_s.h => fmsub_s.h}      |   0
 riscv/insns/{mul_d.h => fmul_d.h}        |   0
 riscv/insns/{mul_s.h => fmul_s.h}        |   0
 riscv/insns/{nmadd_d.h => fnmadd_d.h}    |   0
 riscv/insns/{nmadd_s.h => fnmadd_s.h}    |   0
 riscv/insns/{nmsub_d.h => fnmsub_d.h}    |   0
 riscv/insns/{nmsub_s.h => fnmsub_s.h}    |   0
 riscv/insns/fsel_d.h                     |   3 +
 riscv/insns/fsel_s.h                     |   3 +
 riscv/insns/{sgninj_d.h => fsinj_d.h}    |   0
 riscv/insns/{sgninj_s.h => fsinj_s.h}    |   0
 riscv/insns/{sgninjn_d.h => fsinjn_d.h}  |   0
 riscv/insns/{sgninjn_s.h => fsinjn_s.h}  |   0
 riscv/insns/{sgnmul_d.h => fsmul_d.h}    |   0
 riscv/insns/{sgnmul_s.h => fsmul_s.h}    |   0
 riscv/insns/{sqrt_d.h => fsqrt_d.h}      |   0
 riscv/insns/{sqrt_s.h => fsqrt_s.h}      |   0
 riscv/insns/{sub_d.h => fsub_d.h}        |   0
 riscv/insns/{sub_s.h => fsub_s.h}        |   0
 riscv/insns/{lb.h => l_b.h}              |   0
 riscv/insns/{lbu.h => l_bu.h}            |   0
 riscv/insns/l_d.h                        |   4 +-
 riscv/insns/{lh.h => l_h.h}              |   0
 riscv/insns/{lhu.h => l_hu.h}            |   0
 riscv/insns/{lw.h => l_w.h}              |   0
 riscv/insns/{lwu.h => l_wu.h}            |   0
 riscv/insns/ld.h                         |   2 -
 riscv/insns/lf_d.h                       |   2 +
 riscv/insns/{l_s.h => lf_w.h}            |   0
 riscv/insns/{sb.h => s_b.h}              |   0
 riscv/insns/s_d.h                        |   4 +-
 riscv/insns/{sh.h => s_h.h}              |   0
 riscv/insns/{sw.h => s_w.h}              |   0
 riscv/insns/sd.h                         |   2 -
 riscv/insns/sf_d.h                       |   2 +
 riscv/insns/{s_s.h => sf_w.h}            |   0
 84 files changed, 186 insertions(+), 151 deletions(-)
 rename riscv/insns/{amo_add.h => amoadd_d.h} (100%)
 rename riscv/insns/{amow_add.h => amoadd_w.h} (100%)
 rename riscv/insns/{amo_and.h => amoand_d.h} (100%)
 rename riscv/insns/{amow_and.h => amoand_w.h} (100%)
 rename riscv/insns/{amo_max.h => amomax_d.h} (100%)
 rename riscv/insns/{amow_max.h => amomax_w.h} (100%)
 rename riscv/insns/{amo_maxu.h => amomaxu_d.h} (100%)
 rename riscv/insns/{amow_maxu.h => amomaxu_w.h} (100%)
 rename riscv/insns/{amo_min.h => amomin_d.h} (100%)
 rename riscv/insns/{amow_min.h => amomin_w.h} (100%)
 rename riscv/insns/{amo_minu.h => amominu_d.h} (100%)
 rename riscv/insns/{amow_minu.h => amominu_w.h} (100%)
 rename riscv/insns/{amo_or.h => amoor_d.h} (100%)
 rename riscv/insns/{amow_or.h => amoor_w.h} (100%)
 rename riscv/insns/{amo_swap.h => amoswap_d.h} (100%)
 rename riscv/insns/{amow_swap.h => amoswap_w.h} (100%)
 rename riscv/insns/{add_d.h => fadd_d.h} (100%)
 rename riscv/insns/{add_s.h => fadd_s.h} (100%)
 rename riscv/insns/{c_eq_d.h => fc_eq_d.h} (100%)
 rename riscv/insns/{c_eq_s.h => fc_eq_s.h} (100%)
 rename riscv/insns/{c_le_d.h => fc_le_d.h} (100%)
 rename riscv/insns/{c_le_s.h => fc_le_s.h} (100%)
 rename riscv/insns/{c_lt_d.h => fc_lt_d.h} (100%)
 rename riscv/insns/{c_lt_s.h => fc_lt_s.h} (100%)
 rename riscv/insns/{cvt_d_l.h => fcvt_d_l.h} (100%)
 rename riscv/insns/{cvt_d_s.h => fcvt_d_s.h} (100%)
 rename riscv/insns/{cvt_d_w.h => fcvt_d_w.h} (100%)
 rename riscv/insns/{cvt_l_d.h => fcvt_l_d.h} (100%)
 rename riscv/insns/{cvt_l_s.h => fcvt_l_s.h} (100%)
 rename riscv/insns/{cvt_s_d.h => fcvt_s_d.h} (100%)
 rename riscv/insns/{cvt_s_l.h => fcvt_s_l.h} (100%)
 rename riscv/insns/{cvt_s_w.h => fcvt_s_w.h} (100%)
 rename riscv/insns/{cvt_w_d.h => fcvt_w_d.h} (100%)
 rename riscv/insns/{cvt_w_s.h => fcvt_w_s.h} (100%)
 rename riscv/insns/{cvtu_d_l.h => fcvtu_d_l.h} (100%)
 rename riscv/insns/{cvtu_d_w.h => fcvtu_d_w.h} (100%)
 rename riscv/insns/{cvtu_l_d.h => fcvtu_l_d.h} (100%)
 rename riscv/insns/{cvtu_l_s.h => fcvtu_l_s.h} (100%)
 rename riscv/insns/{cvtu_s_l.h => fcvtu_s_l.h} (100%)
 rename riscv/insns/{cvtu_s_w.h => fcvtu_s_w.h} (100%)
 rename riscv/insns/{cvtu_w_d.h => fcvtu_w_d.h} (100%)
 rename riscv/insns/{cvtu_w_s.h => fcvtu_w_s.h} (100%)
 rename riscv/insns/{div_d.h => fdiv_d.h} (100%)
 rename riscv/insns/{div_s.h => fdiv_s.h} (100%)
 rename riscv/insns/{madd_d.h => fmadd_d.h} (100%)
 rename riscv/insns/{madd_s.h => fmadd_s.h} (100%)
 rename riscv/insns/{msub_d.h => fmsub_d.h} (100%)
 rename riscv/insns/{msub_s.h => fmsub_s.h} (100%)
 rename riscv/insns/{mul_d.h => fmul_d.h} (100%)
 rename riscv/insns/{mul_s.h => fmul_s.h} (100%)
 rename riscv/insns/{nmadd_d.h => fnmadd_d.h} (100%)
 rename riscv/insns/{nmadd_s.h => fnmadd_s.h} (100%)
 rename riscv/insns/{nmsub_d.h => fnmsub_d.h} (100%)
 rename riscv/insns/{nmsub_s.h => fnmsub_s.h} (100%)
 create mode 100644 riscv/insns/fsel_d.h
 create mode 100644 riscv/insns/fsel_s.h
 rename riscv/insns/{sgninj_d.h => fsinj_d.h} (100%)
 rename riscv/insns/{sgninj_s.h => fsinj_s.h} (100%)
 rename riscv/insns/{sgninjn_d.h => fsinjn_d.h} (100%)
 rename riscv/insns/{sgninjn_s.h => fsinjn_s.h} (100%)
 rename riscv/insns/{sgnmul_d.h => fsmul_d.h} (100%)
 rename riscv/insns/{sgnmul_s.h => fsmul_s.h} (100%)
 rename riscv/insns/{sqrt_d.h => fsqrt_d.h} (100%)
 rename riscv/insns/{sqrt_s.h => fsqrt_s.h} (100%)
 rename riscv/insns/{sub_d.h => fsub_d.h} (100%)
 rename riscv/insns/{sub_s.h => fsub_s.h} (100%)
 rename riscv/insns/{lb.h => l_b.h} (100%)
 rename riscv/insns/{lbu.h => l_bu.h} (100%)
 rename riscv/insns/{lh.h => l_h.h} (100%)
 rename riscv/insns/{lhu.h => l_hu.h} (100%)
 rename riscv/insns/{lw.h => l_w.h} (100%)
 rename riscv/insns/{lwu.h => l_wu.h} (100%)
 delete mode 100644 riscv/insns/ld.h
 create mode 100644 riscv/insns/lf_d.h
 rename riscv/insns/{l_s.h => lf_w.h} (100%)
 rename riscv/insns/{sb.h => s_b.h} (100%)
 rename riscv/insns/{sh.h => s_h.h} (100%)
 rename riscv/insns/{sw.h => s_w.h} (100%)
 delete mode 100644 riscv/insns/sd.h
 create mode 100644 riscv/insns/sf_d.h
 rename riscv/insns/{s_s.h => sf_w.h} (100%)

diff --git a/riscv/execute.h b/riscv/execute.h
index b8e396a..88b5a84 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -98,18 +98,47 @@ switch((insn.bits >> 0x0) & 0x7f)
     }
     break;
   }
+  case 0x67:
+  {
+    switch((insn.bits >> 0x7) & 0x7)
+    {
+      case 0x0:
+      {
+        if((insn.bits & 0xfff) == 0x67)
+        {
+          #include "insns/fsel_s.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfff) == 0x1e7)
+        {
+          #include "insns/fsel_d.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x68:
   {
     switch((insn.bits >> 0x7) & 0x7)
     {
       case 0x2:
       {
-        #include "insns/l_s.h"
+        #include "insns/lf_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/l_d.h"
+        #include "insns/lf_d.h"
         break;
       }
       default:
@@ -125,12 +154,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        #include "insns/s_s.h"
+        #include "insns/sf_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/s_d.h"
+        #include "insns/sf_d.h"
         break;
       }
       default:
@@ -146,39 +175,39 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0x1ffff) == 0x1506a)
+        if((insn.bits & 0x1ffff) == 0x606a)
         {
-          #include "insns/c_eq_s.h"
+          #include "insns/fsinjn_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x506a)
+        if((insn.bits & 0x7c1ffff) == 0x1846a)
         {
-          #include "insns/sgninj_s.h"
+          #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa06a)
+        if((insn.bits & 0x3ff1ff) == 0x1306a)
         {
-          #include "insns/cvt_w_s.h"
+          #include "insns/fcvt_s_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xe06a)
+        if((insn.bits & 0x1f1ff) == 0x6a)
         {
-          #include "insns/cvt_s_w.h"
+          #include "insns/fadd_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x6a)
+        if((insn.bits & 0x3ff1ff) == 0xe06a)
         {
-          #include "insns/add_s.h"
+          #include "insns/fcvt_s_w.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x906a)
+        if((insn.bits & 0x3ff1ff) == 0xb06a)
         {
-          #include "insns/cvtu_l_s.h"
+          #include "insns/fcvtu_w_s.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x1846a)
+        if((insn.bits & 0x3ff1ff) == 0x806a)
         {
-          #include "insns/mff_s.h"
+          #include "insns/fcvt_l_s.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x1c46a)
@@ -186,158 +215,153 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/mtf_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x606a)
+        if((insn.bits & 0x1f1ff) == 0x306a)
         {
-          #include "insns/sgninjn_s.h"
+          #include "insns/fdiv_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x806a)
+        if((insn.bits & 0x1ffff) == 0x1606a)
         {
-          #include "insns/cvt_l_s.h"
+          #include "insns/fc_lt_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xf06a)
+        if((insn.bits & 0x1f1ff) == 0x206a)
         {
-          #include "insns/cvtu_s_w.h"
+          #include "insns/fmul_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd06a)
+        if((insn.bits & 0x1ffff) == 0x706a)
         {
-          #include "insns/cvtu_s_l.h"
+          #include "insns/fsmul_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x106a)
+        if((insn.bits & 0x3ff1ff) == 0xa06a)
         {
-          #include "insns/sub_s.h"
+          #include "insns/fcvt_w_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x406a)
+        if((insn.bits & 0x1ffff) == 0x506a)
         {
-          #include "insns/sqrt_s.h"
+          #include "insns/fsinj_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1606a)
+        if((insn.bits & 0x1f1ff) == 0x106a)
         {
-          #include "insns/c_lt_s.h"
+          #include "insns/fsub_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x706a)
+        if((insn.bits & 0x1ffff) == 0x1706a)
         {
-          #include "insns/sgnmul_s.h"
+          #include "insns/fc_le_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xc06a)
+        if((insn.bits & 0x3ff1ff) == 0xf06a)
         {
-          #include "insns/cvt_s_l.h"
+          #include "insns/fcvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x306a)
+        if((insn.bits & 0x3ff1ff) == 0xd06a)
         {
-          #include "insns/div_s.h"
+          #include "insns/fcvtu_s_l.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x1306a)
+        if((insn.bits & 0x3ff1ff) == 0x906a)
         {
-          #include "insns/cvt_s_d.h"
+          #include "insns/fcvtu_l_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1706a)
+        if((insn.bits & 0x3ff1ff) == 0xc06a)
         {
-          #include "insns/c_le_s.h"
+          #include "insns/fcvt_s_l.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x206a)
+        if((insn.bits & 0x3ff1ff) == 0x406a)
         {
-          #include "insns/mul_s.h"
+          #include "insns/fsqrt_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb06a)
+        if((insn.bits & 0x1ffff) == 0x1506a)
         {
-          #include "insns/cvtu_w_s.h"
+          #include "insns/fc_eq_s.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0x3ff1ff) == 0xa1ea)
-        {
-          #include "insns/cvt_w_d.h"
-          break;
-        }
         if((insn.bits & 0x7c1ffff) == 0x185ea)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x51ea)
+        if((insn.bits & 0x1ffff) == 0x61ea)
         {
-          #include "insns/sgninj_d.h"
+          #include "insns/fsinjn_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x31ea)
+        if((insn.bits & 0x3ff1ff) == 0xc1ea)
         {
-          #include "insns/div_d.h"
+          #include "insns/fcvt_d_l.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x151ea)
+        if((insn.bits & 0x3fffff) == 0xe1ea)
         {
-          #include "insns/c_eq_d.h"
+          #include "insns/fcvt_d_w.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd1ea)
+        if((insn.bits & 0x3fffff) == 0x101ea)
         {
-          #include "insns/cvtu_d_l.h"
+          #include "insns/fcvt_d_s.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xf1ea)
+        if((insn.bits & 0x7c1ffff) == 0x195ea)
         {
-          #include "insns/cvtu_d_w.h"
+          #include "insns/mffl_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x91ea)
+        if((insn.bits & 0x7c1ffff) == 0x1a5ea)
         {
-          #include "insns/cvtu_l_d.h"
+          #include "insns/mffh_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x195ea)
+        if((insn.bits & 0x3ff1ff) == 0x81ea)
         {
-          #include "insns/mffl_d.h"
+          #include "insns/fcvt_l_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x71ea)
+        if((insn.bits & 0x3fffff) == 0xf1ea)
         {
-          #include "insns/sgnmul_d.h"
+          #include "insns/fcvtu_d_w.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x1ea)
+        if((insn.bits & 0x1ffff) == 0x161ea)
         {
-          #include "insns/add_d.h"
+          #include "insns/fc_lt_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x1a5ea)
+        if((insn.bits & 0x1f1ff) == 0x21ea)
         {
-          #include "insns/mffh_d.h"
+          #include "insns/fmul_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x171ea)
+        if((insn.bits & 0x1ffff) == 0x151ea)
         {
-          #include "insns/c_le_d.h"
+          #include "insns/fc_eq_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x61ea)
+        if((insn.bits & 0x1ffff) == 0x71ea)
         {
-          #include "insns/sgninjn_d.h"
+          #include "insns/fsmul_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x81ea)
+        if((insn.bits & 0x1ffff) == 0x51ea)
         {
-          #include "insns/cvt_l_d.h"
+          #include "insns/fsinj_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x11ea)
+        if((insn.bits & 0x3ff1ff) == 0xa1ea)
         {
-          #include "insns/sub_d.h"
+          #include "insns/fcvt_w_d.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x1c5ea)
@@ -345,39 +369,44 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/mtf_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x41ea)
+        if((insn.bits & 0x1ffff) == 0x171ea)
         {
-          #include "insns/sqrt_d.h"
+          #include "insns/fc_le_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x101ea)
+        if((insn.bits & 0x3ff1ff) == 0xb1ea)
         {
-          #include "insns/cvt_d_s.h"
+          #include "insns/fcvtu_w_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xe1ea)
+        if((insn.bits & 0x1f1ff) == 0x1ea)
         {
-          #include "insns/cvt_d_w.h"
+          #include "insns/fadd_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xc1ea)
+        if((insn.bits & 0x3ff1ff) == 0x91ea)
         {
-          #include "insns/cvt_d_l.h"
+          #include "insns/fcvtu_l_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x21ea)
+        if((insn.bits & 0x1f1ff) == 0x11ea)
         {
-          #include "insns/mul_d.h"
+          #include "insns/fsub_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb1ea)
+        if((insn.bits & 0x3ff1ff) == 0x41ea)
         {
-          #include "insns/cvtu_w_d.h"
+          #include "insns/fsqrt_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x161ea)
+        if((insn.bits & 0x1f1ff) == 0x31ea)
+        {
+          #include "insns/fdiv_d.h"
+          break;
+        }
+        if((insn.bits & 0x3ff1ff) == 0xd1ea)
         {
-          #include "insns/c_lt_d.h"
+          #include "insns/fcvtu_d_l.h"
           break;
         }
         #include "insns/unimp.h"
@@ -452,12 +481,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/madd_s.h"
+        #include "insns/fmadd_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/madd_d.h"
+        #include "insns/fmadd_d.h"
         break;
       }
       default:
@@ -473,12 +502,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/msub_s.h"
+        #include "insns/fmsub_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/msub_d.h"
+        #include "insns/fmsub_d.h"
         break;
       }
       default:
@@ -494,12 +523,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/nmsub_s.h"
+        #include "insns/fnmsub_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/nmsub_d.h"
+        #include "insns/fnmsub_d.h"
         break;
       }
       default:
@@ -515,12 +544,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/nmadd_s.h"
+        #include "insns/fnmadd_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/nmadd_d.h"
+        #include "insns/fnmadd_d.h"
         break;
       }
       default:
@@ -817,37 +846,37 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/lb.h"
+        #include "insns/l_b.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/lh.h"
+        #include "insns/l_h.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/lw.h"
+        #include "insns/l_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/ld.h"
+        #include "insns/l_d.h"
         break;
       }
       case 0x4:
       {
-        #include "insns/lbu.h"
+        #include "insns/l_bu.h"
         break;
       }
       case 0x5:
       {
-        #include "insns/lhu.h"
+        #include "insns/l_hu.h"
         break;
       }
       case 0x6:
       {
-        #include "insns/lwu.h"
+        #include "insns/l_wu.h"
         break;
       }
       case 0x7:
@@ -872,22 +901,22 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/sb.h"
+        #include "insns/s_b.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/sh.h"
+        #include "insns/s_h.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/sw.h"
+        #include "insns/s_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/sd.h"
+        #include "insns/s_d.h"
         break;
       }
       default:
@@ -903,88 +932,88 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        if((insn.bits & 0x1ffff) == 0x157a)
+        if((insn.bits & 0x1ffff) == 0x197a)
         {
-          #include "insns/amow_max.h"
+          #include "insns/amominu_w.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x97a)
         {
-          #include "insns/amow_and.h"
+          #include "insns/amoand_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x117a)
+        if((insn.bits & 0x1ffff) == 0x1d7a)
         {
-          #include "insns/amow_min.h"
+          #include "insns/amomaxu_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xd7a)
+        if((insn.bits & 0x1ffff) == 0x157a)
         {
-          #include "insns/amow_or.h"
+          #include "insns/amomax_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x197a)
+        if((insn.bits & 0x1ffff) == 0x17a)
         {
-          #include "insns/amow_minu.h"
+          #include "insns/amoadd_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x17a)
+        if((insn.bits & 0x1ffff) == 0xd7a)
         {
-          #include "insns/amow_add.h"
+          #include "insns/amoor_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x57a)
+        if((insn.bits & 0x1ffff) == 0x117a)
         {
-          #include "insns/amow_swap.h"
+          #include "insns/amomin_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d7a)
+        if((insn.bits & 0x1ffff) == 0x57a)
         {
-          #include "insns/amow_maxu.h"
+          #include "insns/amoswap_w.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0x1ffff) == 0x1fa)
+        if((insn.bits & 0x1ffff) == 0x19fa)
         {
-          #include "insns/amo_add.h"
+          #include "insns/amominu_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x5fa)
+        if((insn.bits & 0x1ffff) == 0x9fa)
         {
-          #include "insns/amo_swap.h"
+          #include "insns/amoand_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xdfa)
+        if((insn.bits & 0x1ffff) == 0x1dfa)
         {
-          #include "insns/amo_or.h"
+          #include "insns/amomaxu_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x15fa)
+        if((insn.bits & 0x1ffff) == 0x11fa)
         {
-          #include "insns/amo_max.h"
+          #include "insns/amomin_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x11fa)
+        if((insn.bits & 0x1ffff) == 0x1fa)
         {
-          #include "insns/amo_min.h"
+          #include "insns/amoadd_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x19fa)
+        if((insn.bits & 0x1ffff) == 0x15fa)
         {
-          #include "insns/amo_minu.h"
+          #include "insns/amomax_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x9fa)
+        if((insn.bits & 0x1ffff) == 0xdfa)
         {
-          #include "insns/amo_and.h"
+          #include "insns/amoor_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1dfa)
+        if((insn.bits & 0x1ffff) == 0x5fa)
         {
-          #include "insns/amo_maxu.h"
+          #include "insns/amoswap_d.h"
           break;
         }
         #include "insns/unimp.h"
diff --git a/riscv/insns/amo_add.h b/riscv/insns/amoadd_d.h
similarity index 100%
rename from riscv/insns/amo_add.h
rename to riscv/insns/amoadd_d.h
diff --git a/riscv/insns/amow_add.h b/riscv/insns/amoadd_w.h
similarity index 100%
rename from riscv/insns/amow_add.h
rename to riscv/insns/amoadd_w.h
diff --git a/riscv/insns/amo_and.h b/riscv/insns/amoand_d.h
similarity index 100%
rename from riscv/insns/amo_and.h
rename to riscv/insns/amoand_d.h
diff --git a/riscv/insns/amow_and.h b/riscv/insns/amoand_w.h
similarity index 100%
rename from riscv/insns/amow_and.h
rename to riscv/insns/amoand_w.h
diff --git a/riscv/insns/amo_max.h b/riscv/insns/amomax_d.h
similarity index 100%
rename from riscv/insns/amo_max.h
rename to riscv/insns/amomax_d.h
diff --git a/riscv/insns/amow_max.h b/riscv/insns/amomax_w.h
similarity index 100%
rename from riscv/insns/amow_max.h
rename to riscv/insns/amomax_w.h
diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amomaxu_d.h
similarity index 100%
rename from riscv/insns/amo_maxu.h
rename to riscv/insns/amomaxu_d.h
diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amomaxu_w.h
similarity index 100%
rename from riscv/insns/amow_maxu.h
rename to riscv/insns/amomaxu_w.h
diff --git a/riscv/insns/amo_min.h b/riscv/insns/amomin_d.h
similarity index 100%
rename from riscv/insns/amo_min.h
rename to riscv/insns/amomin_d.h
diff --git a/riscv/insns/amow_min.h b/riscv/insns/amomin_w.h
similarity index 100%
rename from riscv/insns/amow_min.h
rename to riscv/insns/amomin_w.h
diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amominu_d.h
similarity index 100%
rename from riscv/insns/amo_minu.h
rename to riscv/insns/amominu_d.h
diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amominu_w.h
similarity index 100%
rename from riscv/insns/amow_minu.h
rename to riscv/insns/amominu_w.h
diff --git a/riscv/insns/amo_or.h b/riscv/insns/amoor_d.h
similarity index 100%
rename from riscv/insns/amo_or.h
rename to riscv/insns/amoor_d.h
diff --git a/riscv/insns/amow_or.h b/riscv/insns/amoor_w.h
similarity index 100%
rename from riscv/insns/amow_or.h
rename to riscv/insns/amoor_w.h
diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amoswap_d.h
similarity index 100%
rename from riscv/insns/amo_swap.h
rename to riscv/insns/amoswap_d.h
diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amoswap_w.h
similarity index 100%
rename from riscv/insns/amow_swap.h
rename to riscv/insns/amoswap_w.h
diff --git a/riscv/insns/add_d.h b/riscv/insns/fadd_d.h
similarity index 100%
rename from riscv/insns/add_d.h
rename to riscv/insns/fadd_d.h
diff --git a/riscv/insns/add_s.h b/riscv/insns/fadd_s.h
similarity index 100%
rename from riscv/insns/add_s.h
rename to riscv/insns/fadd_s.h
diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/fc_eq_d.h
similarity index 100%
rename from riscv/insns/c_eq_d.h
rename to riscv/insns/fc_eq_d.h
diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/fc_eq_s.h
similarity index 100%
rename from riscv/insns/c_eq_s.h
rename to riscv/insns/fc_eq_s.h
diff --git a/riscv/insns/c_le_d.h b/riscv/insns/fc_le_d.h
similarity index 100%
rename from riscv/insns/c_le_d.h
rename to riscv/insns/fc_le_d.h
diff --git a/riscv/insns/c_le_s.h b/riscv/insns/fc_le_s.h
similarity index 100%
rename from riscv/insns/c_le_s.h
rename to riscv/insns/fc_le_s.h
diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/fc_lt_d.h
similarity index 100%
rename from riscv/insns/c_lt_d.h
rename to riscv/insns/fc_lt_d.h
diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/fc_lt_s.h
similarity index 100%
rename from riscv/insns/c_lt_s.h
rename to riscv/insns/fc_lt_s.h
diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/fcvt_d_l.h
similarity index 100%
rename from riscv/insns/cvt_d_l.h
rename to riscv/insns/fcvt_d_l.h
diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/fcvt_d_s.h
similarity index 100%
rename from riscv/insns/cvt_d_s.h
rename to riscv/insns/fcvt_d_s.h
diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/fcvt_d_w.h
similarity index 100%
rename from riscv/insns/cvt_d_w.h
rename to riscv/insns/fcvt_d_w.h
diff --git a/riscv/insns/cvt_l_d.h b/riscv/insns/fcvt_l_d.h
similarity index 100%
rename from riscv/insns/cvt_l_d.h
rename to riscv/insns/fcvt_l_d.h
diff --git a/riscv/insns/cvt_l_s.h b/riscv/insns/fcvt_l_s.h
similarity index 100%
rename from riscv/insns/cvt_l_s.h
rename to riscv/insns/fcvt_l_s.h
diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/fcvt_s_d.h
similarity index 100%
rename from riscv/insns/cvt_s_d.h
rename to riscv/insns/fcvt_s_d.h
diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/fcvt_s_l.h
similarity index 100%
rename from riscv/insns/cvt_s_l.h
rename to riscv/insns/fcvt_s_l.h
diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/fcvt_s_w.h
similarity index 100%
rename from riscv/insns/cvt_s_w.h
rename to riscv/insns/fcvt_s_w.h
diff --git a/riscv/insns/cvt_w_d.h b/riscv/insns/fcvt_w_d.h
similarity index 100%
rename from riscv/insns/cvt_w_d.h
rename to riscv/insns/fcvt_w_d.h
diff --git a/riscv/insns/cvt_w_s.h b/riscv/insns/fcvt_w_s.h
similarity index 100%
rename from riscv/insns/cvt_w_s.h
rename to riscv/insns/fcvt_w_s.h
diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/fcvtu_d_l.h
similarity index 100%
rename from riscv/insns/cvtu_d_l.h
rename to riscv/insns/fcvtu_d_l.h
diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/fcvtu_d_w.h
similarity index 100%
rename from riscv/insns/cvtu_d_w.h
rename to riscv/insns/fcvtu_d_w.h
diff --git a/riscv/insns/cvtu_l_d.h b/riscv/insns/fcvtu_l_d.h
similarity index 100%
rename from riscv/insns/cvtu_l_d.h
rename to riscv/insns/fcvtu_l_d.h
diff --git a/riscv/insns/cvtu_l_s.h b/riscv/insns/fcvtu_l_s.h
similarity index 100%
rename from riscv/insns/cvtu_l_s.h
rename to riscv/insns/fcvtu_l_s.h
diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/fcvtu_s_l.h
similarity index 100%
rename from riscv/insns/cvtu_s_l.h
rename to riscv/insns/fcvtu_s_l.h
diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/fcvtu_s_w.h
similarity index 100%
rename from riscv/insns/cvtu_s_w.h
rename to riscv/insns/fcvtu_s_w.h
diff --git a/riscv/insns/cvtu_w_d.h b/riscv/insns/fcvtu_w_d.h
similarity index 100%
rename from riscv/insns/cvtu_w_d.h
rename to riscv/insns/fcvtu_w_d.h
diff --git a/riscv/insns/cvtu_w_s.h b/riscv/insns/fcvtu_w_s.h
similarity index 100%
rename from riscv/insns/cvtu_w_s.h
rename to riscv/insns/fcvtu_w_s.h
diff --git a/riscv/insns/div_d.h b/riscv/insns/fdiv_d.h
similarity index 100%
rename from riscv/insns/div_d.h
rename to riscv/insns/fdiv_d.h
diff --git a/riscv/insns/div_s.h b/riscv/insns/fdiv_s.h
similarity index 100%
rename from riscv/insns/div_s.h
rename to riscv/insns/fdiv_s.h
diff --git a/riscv/insns/madd_d.h b/riscv/insns/fmadd_d.h
similarity index 100%
rename from riscv/insns/madd_d.h
rename to riscv/insns/fmadd_d.h
diff --git a/riscv/insns/madd_s.h b/riscv/insns/fmadd_s.h
similarity index 100%
rename from riscv/insns/madd_s.h
rename to riscv/insns/fmadd_s.h
diff --git a/riscv/insns/msub_d.h b/riscv/insns/fmsub_d.h
similarity index 100%
rename from riscv/insns/msub_d.h
rename to riscv/insns/fmsub_d.h
diff --git a/riscv/insns/msub_s.h b/riscv/insns/fmsub_s.h
similarity index 100%
rename from riscv/insns/msub_s.h
rename to riscv/insns/fmsub_s.h
diff --git a/riscv/insns/mul_d.h b/riscv/insns/fmul_d.h
similarity index 100%
rename from riscv/insns/mul_d.h
rename to riscv/insns/fmul_d.h
diff --git a/riscv/insns/mul_s.h b/riscv/insns/fmul_s.h
similarity index 100%
rename from riscv/insns/mul_s.h
rename to riscv/insns/fmul_s.h
diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/fnmadd_d.h
similarity index 100%
rename from riscv/insns/nmadd_d.h
rename to riscv/insns/fnmadd_d.h
diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/fnmadd_s.h
similarity index 100%
rename from riscv/insns/nmadd_s.h
rename to riscv/insns/fnmadd_s.h
diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/fnmsub_d.h
similarity index 100%
rename from riscv/insns/nmsub_d.h
rename to riscv/insns/fnmsub_d.h
diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/fnmsub_s.h
similarity index 100%
rename from riscv/insns/nmsub_s.h
rename to riscv/insns/fnmsub_s.h
diff --git a/riscv/insns/fsel_d.h b/riscv/insns/fsel_d.h
new file mode 100644
index 0000000..fe74bcd
--- /dev/null
+++ b/riscv/insns/fsel_d.h
@@ -0,0 +1,3 @@
+require_fp;
+FRD = !f64_eq(FRS1, 0) ? FRS2 : FRS3;
+set_fp_exceptions;
diff --git a/riscv/insns/fsel_s.h b/riscv/insns/fsel_s.h
new file mode 100644
index 0000000..78b8f5d
--- /dev/null
+++ b/riscv/insns/fsel_s.h
@@ -0,0 +1,3 @@
+require_fp;
+FRD = !f32_eq(FRS1, 0) ? FRS2 : FRS3;
+set_fp_exceptions;
diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/fsinj_d.h
similarity index 100%
rename from riscv/insns/sgninj_d.h
rename to riscv/insns/fsinj_d.h
diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/fsinj_s.h
similarity index 100%
rename from riscv/insns/sgninj_s.h
rename to riscv/insns/fsinj_s.h
diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/fsinjn_d.h
similarity index 100%
rename from riscv/insns/sgninjn_d.h
rename to riscv/insns/fsinjn_d.h
diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/fsinjn_s.h
similarity index 100%
rename from riscv/insns/sgninjn_s.h
rename to riscv/insns/fsinjn_s.h
diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/fsmul_d.h
similarity index 100%
rename from riscv/insns/sgnmul_d.h
rename to riscv/insns/fsmul_d.h
diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/fsmul_s.h
similarity index 100%
rename from riscv/insns/sgnmul_s.h
rename to riscv/insns/fsmul_s.h
diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/fsqrt_d.h
similarity index 100%
rename from riscv/insns/sqrt_d.h
rename to riscv/insns/fsqrt_d.h
diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/fsqrt_s.h
similarity index 100%
rename from riscv/insns/sqrt_s.h
rename to riscv/insns/fsqrt_s.h
diff --git a/riscv/insns/sub_d.h b/riscv/insns/fsub_d.h
similarity index 100%
rename from riscv/insns/sub_d.h
rename to riscv/insns/fsub_d.h
diff --git a/riscv/insns/sub_s.h b/riscv/insns/fsub_s.h
similarity index 100%
rename from riscv/insns/sub_s.h
rename to riscv/insns/fsub_s.h
diff --git a/riscv/insns/lb.h b/riscv/insns/l_b.h
similarity index 100%
rename from riscv/insns/lb.h
rename to riscv/insns/l_b.h
diff --git a/riscv/insns/lbu.h b/riscv/insns/l_bu.h
similarity index 100%
rename from riscv/insns/lbu.h
rename to riscv/insns/l_bu.h
diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
index 123dea4..940d348 100644
--- a/riscv/insns/l_d.h
+++ b/riscv/insns/l_d.h
@@ -1,2 +1,2 @@
-require_fp;
-FRD = mmu.load_int64(RS1+SIMM);
+require_xpr64;
+RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lh.h b/riscv/insns/l_h.h
similarity index 100%
rename from riscv/insns/lh.h
rename to riscv/insns/l_h.h
diff --git a/riscv/insns/lhu.h b/riscv/insns/l_hu.h
similarity index 100%
rename from riscv/insns/lhu.h
rename to riscv/insns/l_hu.h
diff --git a/riscv/insns/lw.h b/riscv/insns/l_w.h
similarity index 100%
rename from riscv/insns/lw.h
rename to riscv/insns/l_w.h
diff --git a/riscv/insns/lwu.h b/riscv/insns/l_wu.h
similarity index 100%
rename from riscv/insns/lwu.h
rename to riscv/insns/l_wu.h
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
deleted file mode 100644
index 940d348..0000000
--- a/riscv/insns/ld.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lf_d.h b/riscv/insns/lf_d.h
new file mode 100644
index 0000000..123dea4
--- /dev/null
+++ b/riscv/insns/lf_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/l_s.h b/riscv/insns/lf_w.h
similarity index 100%
rename from riscv/insns/l_s.h
rename to riscv/insns/lf_w.h
diff --git a/riscv/insns/sb.h b/riscv/insns/s_b.h
similarity index 100%
rename from riscv/insns/sb.h
rename to riscv/insns/s_b.h
diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index 113398e..2009149 100644
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
-require_fp;
-mmu.store_uint64(RS1+BIMM, FRS2);
+require_xpr64;
+mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/sh.h b/riscv/insns/s_h.h
similarity index 100%
rename from riscv/insns/sh.h
rename to riscv/insns/s_h.h
diff --git a/riscv/insns/sw.h b/riscv/insns/s_w.h
similarity index 100%
rename from riscv/insns/sw.h
rename to riscv/insns/s_w.h
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
deleted file mode 100644
index 2009149..0000000
--- a/riscv/insns/sd.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/sf_d.h b/riscv/insns/sf_d.h
new file mode 100644
index 0000000..113398e
--- /dev/null
+++ b/riscv/insns/sf_d.h
@@ -0,0 +1,2 @@
+require_fp;
+mmu.store_uint64(RS1+BIMM, FRS2);
diff --git a/riscv/insns/s_s.h b/riscv/insns/sf_w.h
similarity index 100%
rename from riscv/insns/s_s.h
rename to riscv/insns/sf_w.h
-- 
2.30.2