From f01e569f6061be6677dd4874812d2a39bd45fe2d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 23 Apr 2021 15:13:58 +0100 Subject: [PATCH] resolving imports changing over --- src/openpower/decoder/decode2execute1.py | 6 +- src/openpower/decoder/formal/proof_decoder.py | 6 +- .../decoder/formal/proof_decoder2.py | 6 +- src/openpower/decoder/helpers.py | 9 +- src/openpower/decoder/isa/caller.py | 20 +-- src/openpower/decoder/isa/mem.py | 4 +- src/openpower/decoder/isa/radixmmu.py | 8 +- src/openpower/decoder/isa/test_caller.py | 16 +- .../decoder/isa/test_caller_radix.py | 18 +-- .../decoder/isa/test_caller_setvl.py | 22 +-- .../decoder/isa/test_caller_svp64.py | 22 +-- .../isa/test_caller_svp64_predication.py | 22 +-- src/openpower/decoder/power_decoder.py | 8 +- src/openpower/decoder/power_decoder2.py | 30 ++-- src/openpower/decoder/power_fields.py | 2 +- src/openpower/decoder/power_fieldsn.py | 2 +- src/openpower/decoder/power_pseudo.py | 10 +- src/openpower/decoder/power_regspec_map.py | 2 +- src/openpower/decoder/power_svp64.py | 2 +- src/openpower/decoder/power_svp64_extra.py | 4 +- src/openpower/decoder/power_svp64_prefix.py | 2 +- src/openpower/decoder/power_svp64_rm.py | 6 +- src/openpower/decoder/pseudo/lexer.py | 2 +- src/openpower/decoder/pseudo/parser.py | 6 +- src/openpower/decoder/selectable_int.py | 2 +- .../decoder/test/test_decoder_gas.py | 8 +- .../decoder/test/test_power_decoder.py | 4 +- src/openpower/endian.py | 5 + src/openpower/simulator/program.py | 2 +- src/openpower/simulator/test_div_sim.py | 16 +- .../simulator/test_helloworld_sim.py | 18 +-- src/openpower/simulator/test_mul_sim.py | 18 +-- src/openpower/simulator/test_shift_sim.py | 18 +-- src/openpower/simulator/test_sim.py | 16 +- src/openpower/simulator/test_trap_sim.py | 18 +-- src/openpower/state.py | 2 +- src/openpower/sv/trans/svp64.py | 10 +- src/openpower/test/common.py | 138 ++++++++++++++++++ 38 files changed, 327 insertions(+), 183 deletions(-) create mode 100644 src/openpower/endian.py create mode 100644 src/openpower/test/common.py diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py index 6333dcdf..0bb7c641 100644 --- a/src/openpower/decoder/decode2execute1.py +++ b/src/openpower/decoder/decode2execute1.py @@ -5,10 +5,10 @@ based on Anton Blanchard microwatt decode2.vhdl """ from nmigen import Signal, Record from nmutil.iocontrol import RecordObject -from soc.decoder.power_enums import (MicrOp, CryIn, Function, +from openpower.decoder.power_enums import (MicrOp, CryIn, Function, SPRfull, SPRreduced, LDSTMode) -from soc.consts import TT -from soc.experiment.mem_types import LDSTException +from openpower.consts import TT +from openpower.exceptions import LDSTException class Data(Record): diff --git a/src/openpower/decoder/formal/proof_decoder.py b/src/openpower/decoder/formal/proof_decoder.py index 5abd9182..ce19a426 100644 --- a/src/openpower/decoder/formal/proof_decoder.py +++ b/src/openpower/decoder/formal/proof_decoder.py @@ -2,12 +2,12 @@ from nmigen import Module, Signal, Elaboratable, Cat from nmigen.asserts import Assert, AnyConst, Assume from nmutil.formaltest import FHDLTestCase -from soc.decoder.power_decoder import create_pdecode, PowerOp -from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, +from openpower.decoder.power_decoder import create_pdecode, PowerOp +from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, Function, LdstLen, CryIn, MicrOp, SPR, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2, +from openpower.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest import pdb diff --git a/src/openpower/decoder/formal/proof_decoder2.py b/src/openpower/decoder/formal/proof_decoder2.py index b7ac61f7..d20c28f1 100644 --- a/src/openpower/decoder/formal/proof_decoder2.py +++ b/src/openpower/decoder/formal/proof_decoder2.py @@ -2,11 +2,11 @@ from nmigen import Module, Signal, Elaboratable, Cat, Repl from nmigen.asserts import Assert, AnyConst from nmutil.formaltest import FHDLTestCase -from soc.decoder.power_decoder import create_pdecode, PowerOp -from soc.decoder.power_enums import (In1Sel, In2Sel, In3Sel, +from openpower.decoder.power_decoder import create_pdecode, PowerOp +from openpower.decoder.power_enums import (In1Sel, In2Sel, In3Sel, OutSel, RC, Form, MicrOp, SPR) -from soc.decoder.power_decoder2 import (PowerDecode2, +from openpower.decoder.power_decoder2 import (PowerDecode2, Decode2ToExecute1Type) import unittest diff --git a/src/openpower/decoder/helpers.py b/src/openpower/decoder/helpers.py index 6f63cc3d..c8d0044d 100644 --- a/src/openpower/decoder/helpers.py +++ b/src/openpower/decoder/helpers.py @@ -1,10 +1,10 @@ import unittest -from soc.decoder.selectable_int import SelectableInt, onebit +from openpower.decoder.selectable_int import SelectableInt, onebit from nmutil.divmod import trunc_divs, trunc_rems from operator import floordiv, mod -from soc.decoder.selectable_int import selectltu as ltu -from soc.decoder.selectable_int import selectgtu as gtu -from soc.decoder.selectable_int import check_extsign +from openpower.decoder.selectable_int import selectltu as ltu +from openpower.decoder.selectable_int import selectgtu as gtu +from openpower.decoder.selectable_int import check_extsign trunc_div = floordiv trunc_rem = mod @@ -25,6 +25,7 @@ def exts(value, bits): def EXTS(value): """ extends sign bit out from current MSB to all 256 bits """ + print ("EXTS", value, type(value)) assert isinstance(value, SelectableInt) return SelectableInt(exts(value.value, value.bits) & ((1 << 256)-1), 256) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 315db251..2f9dfa87 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -16,24 +16,24 @@ related bugs: from nmigen.back.pysim import Settle from functools import wraps from copy import copy -from soc.decoder.orderedset import OrderedSet -from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) -from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits, +from openpower.decoder.power_enums import (spr_dict, spr_byname, XER_bits, insns, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, CROutSel, SVP64RMMode, SVP64PredMode, SVP64PredInt, SVP64PredCR) -from soc.decoder.power_enums import SVPtype +from openpower.decoder.power_enums import SVPtype -from soc.decoder.helpers import exts, gtu, ltu, undefined -from soc.consts import PIb, MSRb # big-endian (PowerISA versions) -from soc.consts import SVP64CROffs -from soc.decoder.power_svp64 import SVP64RM, decode_extra +from openpower.decoder.helpers import exts, gtu, ltu, undefined +from openpower.consts import PIb, MSRb # big-endian (PowerISA versions) +from openpower.consts import SVP64CROffs +from openpower.decoder.power_svp64 import SVP64RM, decode_extra -from soc.decoder.isa.radixmmu import RADIX -from soc.decoder.isa.mem import Mem, swap_order +from openpower.decoder.isa.radixmmu import RADIX +from openpower.decoder.isa.mem import Mem, swap_order from collections import namedtuple import math diff --git a/src/openpower/decoder/isa/mem.py b/src/openpower/decoder/isa/mem.py index 15df1cbd..c92d70ad 100644 --- a/src/openpower/decoder/isa/mem.py +++ b/src/openpower/decoder/isa/mem.py @@ -13,10 +13,10 @@ related bugs: """ from copy import copy -from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, +from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) -from soc.decoder.helpers import exts, gtu, ltu, undefined +from openpower.decoder.helpers import exts, gtu, ltu, undefined import math import sys diff --git a/src/openpower/decoder/isa/radixmmu.py b/src/openpower/decoder/isa/radixmmu.py index bd814457..04fb775d 100644 --- a/src/openpower/decoder/isa/radixmmu.py +++ b/src/openpower/decoder/isa/radixmmu.py @@ -15,11 +15,11 @@ related bugs: #from nmigen.back.pysim import Settle from copy import copy -from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt, +from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt, selectconcat) -from soc.decoder.helpers import exts, gtu, ltu, undefined -from soc.decoder.isa.mem import Mem -from soc.consts import MSRb # big-endian (PowerISA versions) +from openpower.decoder.helpers import exts, gtu, ltu, undefined +from openpower.decoder.isa.mem import Mem +from openpower.consts import MSRb # big-endian (PowerISA versions) import math import sys diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py index 77b54c7c..00856352 100644 --- a/src/openpower/decoder/isa/test_caller.py +++ b/src/openpower/decoder/isa/test_caller.py @@ -2,14 +2,14 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.isa.caller import ISACaller -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.decoder.isa.caller import ISACaller, inject -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.orderedset import OrderedSet -from soc.decoder.isa.all import ISA +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, inject +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA class Register: diff --git a/src/openpower/decoder/isa/test_caller_radix.py b/src/openpower/decoder/isa/test_caller_radix.py index 26c813d0..d5fe3ef1 100644 --- a/src/openpower/decoder/isa/test_caller_radix.py +++ b/src/openpower/decoder/isa/test_caller_radix.py @@ -2,15 +2,15 @@ from nmigen import Module, Signal #from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.isa.caller import ISACaller -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.decoder.isa.caller import ISACaller, inject, RADIX -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.orderedset import OrderedSet -from soc.decoder.isa.all import ISA -from soc.decoder.isa.test_caller import run_tst +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, inject, RADIX +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import run_tst from copy import deepcopy diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index ad7991f1..0a66dfeb 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -2,17 +2,17 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.isa.caller import ISACaller -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.decoder.isa.caller import ISACaller, SVP64State -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.orderedset import OrderedSet -from soc.decoder.isa.all import ISA -from soc.decoder.isa.test_caller import Register, run_tst -from soc.sv.trans.svp64 import SVP64Asm -from soc.consts import SVP64CROffs +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.sv.trans.svp64 import SVP64Asm +from openpower.consts import SVP64CROffs from copy import deepcopy class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py index 7cc04f40..05bc22bb 100644 --- a/src/openpower/decoder/isa/test_caller_svp64.py +++ b/src/openpower/decoder/isa/test_caller_svp64.py @@ -2,17 +2,17 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.isa.caller import ISACaller -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.decoder.isa.caller import ISACaller, SVP64State -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.orderedset import OrderedSet -from soc.decoder.isa.all import ISA -from soc.decoder.isa.test_caller import Register, run_tst -from soc.sv.trans.svp64 import SVP64Asm -from soc.consts import SVP64CROffs +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.sv.trans.svp64 import SVP64Asm +from openpower.consts import SVP64CROffs from copy import deepcopy class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index 20b7c278..49bd533e 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -2,17 +2,17 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.isa.caller import ISACaller -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.decoder.isa.caller import ISACaller, SVP64State -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.orderedset import OrderedSet -from soc.decoder.isa.all import ISA -from soc.decoder.isa.test_caller import Register, run_tst -from soc.sv.trans.svp64 import SVP64Asm -from soc.consts import SVP64CROffs +from openpower.decoder.isa.caller import ISACaller +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.decoder.isa.caller import ISACaller, SVP64State +from openpower.decoder.selectable_int import SelectableInt +from openpower.decoder.orderedset import OrderedSet +from openpower.decoder.isa.all import ISA +from openpower.decoder.isa.test_caller import Register, run_tst +from openpower.sv.trans.svp64 import SVP64Asm +from openpower.consts import SVP64CROffs from copy import deepcopy class DecoderTestCase(FHDLTestCase): diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py index eb6df3cf..9bfac943 100644 --- a/src/openpower/decoder/power_decoder.py +++ b/src/openpower/decoder/power_decoder.py @@ -90,16 +90,16 @@ import gc from collections import namedtuple from nmigen import Module, Elaboratable, Signal, Cat, Mux from nmigen.cli import rtlil -from soc.decoder.power_enums import (Function, Form, MicrOp, +from openpower.decoder.power_enums import (Function, Form, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, SVEXTRA, SVEtype, SVPtype, # Simple-V RC, LdstLen, LDSTMode, CryIn, single_bit_flags, CRInSel, CROutSel, get_signal_name, default_values, insns, asmidx) -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SigDecode, SignalBitRange -from soc.decoder.power_svp64 import SVP64RM +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SigDecode, SignalBitRange +from openpower.decoder.power_svp64 import SVP64RM # key data structure in which the POWER decoder is specified, # in a hierarchical fashion diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index c0d523d6..a220a3e1 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -10,36 +10,36 @@ from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record from nmigen.cli import rtlil from nmutil.util import sel -from soc.regfile.regfiles import XERRegs - from nmutil.picker import PriorityPicker from nmutil.iocontrol import RecordObject from nmutil.extend import exts -from soc.experiment.mem_types import LDSTException +from openpower.exceptions import LDSTException -from soc.decoder.power_svp64_prefix import SVP64PrefixDecoder -from soc.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra -from soc.decoder.power_svp64_rm import SVP64RMModeDecode -from soc.decoder.power_regspec_map import regspec_decode_read -from soc.decoder.power_regspec_map import regspec_decode_write -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.power_enums import (MicrOp, CryIn, Function, +from openpower.decoder.power_svp64_prefix import SVP64PrefixDecoder +from openpower.decoder.power_svp64_extra import SVP64CRExtra, SVP64RegExtra +from openpower.decoder.power_svp64_rm import SVP64RMModeDecode +from openpower.decoder.power_regspec_map import regspec_decode_read +from openpower.decoder.power_regspec_map import regspec_decode_write +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_enums import (MicrOp, CryIn, Function, CRInSel, CROutSel, LdstLen, In1Sel, In2Sel, In3Sel, OutSel, SPRfull, SPRreduced, RC, LDSTMode, SVEXTRA, SVEtype, SVPtype) -from soc.decoder.decode2execute1 import (Decode2ToExecute1Type, Data, +from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data, Decode2ToOperand) -from soc.sv.svp64 import SVP64Rec -from soc.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field, +from openpower.sv.svp64 import SVP64Rec +from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field, SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs) from soc.regfile.regfiles import FastRegs -from soc.consts import TT -from soc.config.state import CoreState +from openpower.consts import TT +from openpower.state import CoreState from soc.regfile.util import spr_to_fast +from soc.regfile.regfiles import XERRegs + def decode_spr_num(spr): diff --git a/src/openpower/decoder/power_fields.py b/src/openpower/decoder/power_fields.py index d0fe85cb..9cc7d436 100644 --- a/src/openpower/decoder/power_fields.py +++ b/src/openpower/decoder/power_fields.py @@ -1,5 +1,5 @@ from collections import OrderedDict, namedtuple -from soc.decoder.power_enums import find_wiki_file +from openpower.decoder.power_enums import find_wiki_file class BitRange(OrderedDict): diff --git a/src/openpower/decoder/power_fieldsn.py b/src/openpower/decoder/power_fieldsn.py index 852dd15b..e0a02bae 100644 --- a/src/openpower/decoder/power_fieldsn.py +++ b/src/openpower/decoder/power_fieldsn.py @@ -1,5 +1,5 @@ from collections import OrderedDict -from soc.decoder.power_fields import DecodeFields, BitRange +from openpower.decoder.power_fields import DecodeFields, BitRange from nmigen import Module, Elaboratable, Signal, Cat from nmigen.cli import rtlil from copy import deepcopy diff --git a/src/openpower/decoder/power_pseudo.py b/src/openpower/decoder/power_pseudo.py index 3e02cb78..eb87b626 100644 --- a/src/openpower/decoder/power_pseudo.py +++ b/src/openpower/decoder/power_pseudo.py @@ -15,13 +15,13 @@ from ply import lex, yacc import astor import ast -from soc.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder import create_pdecode from nmigen.back.pysim import Simulator, Delay from nmigen import Module, Signal -from soc.decoder.pseudo.parser import GardenSnakeCompiler -from soc.decoder.selectable_int import SelectableInt, selectconcat -from soc.decoder.isa.caller import GPR, Mem +from openpower.decoder.pseudo.parser import GardenSnakeCompiler +from openpower.decoder.selectable_int import SelectableInt, selectconcat +from openpower.decoder.isa.caller import GPR, Mem ####### Test code ####### @@ -256,7 +256,7 @@ def test(): print("args", args) print("-->", " ".join(map(str, args))) - from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK, + from openpower.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK, trunc_div, trunc_rem) d = {} diff --git a/src/openpower/decoder/power_regspec_map.py b/src/openpower/decoder/power_regspec_map.py index 05ff4814..0f5bce32 100644 --- a/src/openpower/decoder/power_regspec_map.py +++ b/src/openpower/decoder/power_regspec_map.py @@ -36,7 +36,7 @@ see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ from nmigen import Const from soc.regfile.regfiles import XERRegs, FastRegs, StateRegs -from soc.decoder.power_enums import CryIn +from openpower.decoder.power_enums import CryIn def regspec_decode_read(e, regfile, name): diff --git a/src/openpower/decoder/power_svp64.py b/src/openpower/decoder/power_svp64.py index 167053c9..3e3332ea 100644 --- a/src/openpower/decoder/power_svp64.py +++ b/src/openpower/decoder/power_svp64.py @@ -2,7 +2,7 @@ # Copyright (C) 2021 Luke Kenneth Casson Leighton # Funded by NLnet http://nlnet.nl -from soc.decoder.power_enums import get_csv, find_wiki_dir +from openpower.decoder.power_enums import get_csv, find_wiki_dir import os # identifies register by type diff --git a/src/openpower/decoder/power_svp64_extra.py b/src/openpower/decoder/power_svp64_extra.py index 02c0bfd5..8a8a3f77 100644 --- a/src/openpower/decoder/power_svp64_extra.py +++ b/src/openpower/decoder/power_svp64_extra.py @@ -6,8 +6,8 @@ from nmigen.cli import rtlil from nmutil.util import sel -from soc.decoder.power_enums import (SVEXTRA, SVEtype) -from soc.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field, +from openpower.decoder.power_enums import (SVEXTRA, SVEtype) +from openpower.consts import (SPEC, EXTRA2, EXTRA3, SVP64P, field, SPEC_SIZE, SPECb, SPEC_AUG_SIZE, SVP64CROffs) diff --git a/src/openpower/decoder/power_svp64_prefix.py b/src/openpower/decoder/power_svp64_prefix.py index 13352ebf..f95d97fe 100644 --- a/src/openpower/decoder/power_svp64_prefix.py +++ b/src/openpower/decoder/power_svp64_prefix.py @@ -6,7 +6,7 @@ from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat from nmigen.cli import rtlil from nmutil.util import sel -from soc.consts import SVP64P +from openpower.consts import SVP64P # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/ # identifies if an instruction is a SVP64-encoded prefix, and extracts diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py index ac29159a..261ed5b9 100644 --- a/src/openpower/decoder/power_svp64_rm.py +++ b/src/openpower/decoder/power_svp64_rm.py @@ -17,10 +17,10 @@ https://libre-soc.org/openpower/sv/svp64/ """ from nmigen import Elaboratable, Module, Signal, Const -from soc.decoder.power_enums import (SVP64RMMode, Function, SVPtype, +from openpower.decoder.power_enums import (SVP64RMMode, Function, SVPtype, SVP64PredMode, SVP64sat) -from soc.consts import EXTRA3, SVP64MODE -from soc.sv.svp64 import SVP64Rec +from openpower.consts import EXTRA3, SVP64MODE +from openpower.sv.svp64 import SVP64Rec from nmutil.util import sel diff --git a/src/openpower/decoder/pseudo/lexer.py b/src/openpower/decoder/pseudo/lexer.py index 43aab336..b420798b 100644 --- a/src/openpower/decoder/pseudo/lexer.py +++ b/src/openpower/decoder/pseudo/lexer.py @@ -10,7 +10,7 @@ # Modifications for inclusion in PLY distribution from copy import copy from ply import lex -from soc.decoder.selectable_int import SelectableInt +from openpower.decoder.selectable_int import SelectableInt # I implemented INDENT / DEDENT generation as a post-processing filter diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py index 54b2635c..0e671960 100644 --- a/src/openpower/decoder/pseudo/parser.py +++ b/src/openpower/decoder/pseudo/parser.py @@ -13,9 +13,9 @@ from ply import lex, yacc import astor from copy import deepcopy -from soc.decoder.power_decoder import create_pdecode -from soc.decoder.pseudo.lexer import IndentLexer -from soc.decoder.orderedset import OrderedSet +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.pseudo.lexer import IndentLexer +from openpower.decoder.orderedset import OrderedSet # I use the Python AST #from compiler import ast diff --git a/src/openpower/decoder/selectable_int.py b/src/openpower/decoder/selectable_int.py index 152764ca..2afe50e6 100644 --- a/src/openpower/decoder/selectable_int.py +++ b/src/openpower/decoder/selectable_int.py @@ -1,6 +1,6 @@ import unittest from copy import copy -from soc.decoder.power_fields import BitRange +from openpower.decoder.power_fields import BitRange from operator import (add, sub, mul, floordiv, truediv, mod, or_, and_, xor, neg, inv, lshift, rshift) diff --git a/src/openpower/decoder/test/test_decoder_gas.py b/src/openpower/decoder/test/test_decoder_gas.py index f65abfac..fdbf8a31 100644 --- a/src/openpower/decoder/test/test_decoder_gas.py +++ b/src/openpower/decoder/test/test_decoder_gas.py @@ -6,14 +6,14 @@ from nmutil.sim_tmp_alternative import Simulator, Delay from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.gas import get_assembled_instruction +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.gas import get_assembled_instruction import random diff --git a/src/openpower/decoder/test/test_power_decoder.py b/src/openpower/decoder/test/test_power_decoder.py index 0a18c77b..8ee9a554 100644 --- a/src/openpower/decoder/test/test_power_decoder.py +++ b/src/openpower/decoder/test/test_power_decoder.py @@ -8,8 +8,8 @@ from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import os import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, CRInSel, CROutSel, OutSel, RC, LdstLen, CryIn, diff --git a/src/openpower/endian.py b/src/openpower/endian.py new file mode 100644 index 00000000..eb6e0c3f --- /dev/null +++ b/src/openpower/endian.py @@ -0,0 +1,5 @@ +global bigendian +bigendian = 0 + +def set_endian_mode(mode): + bigendian = mode diff --git a/src/openpower/simulator/program.py b/src/openpower/simulator/program.py index c55a67d1..f289abe5 100644 --- a/src/openpower/simulator/program.py +++ b/src/openpower/simulator/program.py @@ -15,7 +15,7 @@ import os import sys from io import BytesIO -from soc.simulator.envcmds import cmds +from openpower.simulator.envcmds import cmds filedir = os.path.dirname(os.path.realpath(__file__)) memmap = os.path.join(filedir, "memmap") diff --git a/src/openpower/simulator/test_div_sim.py b/src/openpower/simulator/test_div_sim.py index 171af5c1..394c1a96 100644 --- a/src/openpower/simulator/test_div_sim.py +++ b/src/openpower/simulator/test_div_sim.py @@ -2,18 +2,18 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.simulator.test_sim import DecoderBase +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.simulator.test_sim import DecoderBase diff --git a/src/openpower/simulator/test_helloworld_sim.py b/src/openpower/simulator/test_helloworld_sim.py index d1130437..85cfe4aa 100644 --- a/src/openpower/simulator/test_helloworld_sim.py +++ b/src/openpower/simulator/test_helloworld_sim.py @@ -2,19 +2,19 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.simulator.test_sim import DecoderBase -from soc.config.endian import bigendian +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.simulator.test_sim import DecoderBase +from openpower.endian import bigendian class HelloTestCases(FHDLTestCase): diff --git a/src/openpower/simulator/test_mul_sim.py b/src/openpower/simulator/test_mul_sim.py index 6d251056..d5fbc05c 100644 --- a/src/openpower/simulator/test_mul_sim.py +++ b/src/openpower/simulator/test_mul_sim.py @@ -2,19 +2,19 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.simulator.test_sim import DecoderBase -from soc.config.endian import bigendian +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.simulator.test_sim import DecoderBase +from openpower.endian import bigendian diff --git a/src/openpower/simulator/test_shift_sim.py b/src/openpower/simulator/test_shift_sim.py index e1642105..bed9bf45 100644 --- a/src/openpower/simulator/test_shift_sim.py +++ b/src/openpower/simulator/test_shift_sim.py @@ -2,19 +2,19 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.simulator.test_sim import DecoderBase -from soc.config.endian import bigendian +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.simulator.test_sim import DecoderBase +from openpower.endian import bigendian diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py index 4d586fa7..a18b8bce 100644 --- a/src/openpower/simulator/test_sim.py +++ b/src/openpower/simulator/test_sim.py @@ -2,18 +2,18 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.config.endian import bigendian +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.endian import bigendian class AttnTestCase(FHDLTestCase): diff --git a/src/openpower/simulator/test_trap_sim.py b/src/openpower/simulator/test_trap_sim.py index 1c794826..b6c95803 100644 --- a/src/openpower/simulator/test_trap_sim.py +++ b/src/openpower/simulator/test_trap_sim.py @@ -2,19 +2,19 @@ from nmigen import Module, Signal from nmigen.back.pysim import Simulator, Delay, Settle from nmutil.formaltest import FHDLTestCase import unittest -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_enums import (Function, MicrOp, +from openpower.decoder.power_decoder import (create_pdecode) +from openpower.decoder.power_enums import (Function, MicrOp, In1Sel, In2Sel, In3Sel, OutSel, RC, LdstLen, CryIn, single_bit_flags, Form, SPR, get_signal_name, get_csv) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.simulator.program import Program -from soc.simulator.qemu import run_program -from soc.decoder.isa.all import ISA -from soc.fu.test.common import TestCase -from soc.simulator.test_sim import DecoderBase -from soc.config.endian import bigendian +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.simulator.program import Program +from openpower.simulator.qemu import run_program +from openpower.decoder.isa.all import ISA +from openpower.test.common import TestCase +from openpower.simulator.test_sim import DecoderBase +from openpower.endian import bigendian #XXX HACK! class TrapSimTestCases(FHDLTestCase): diff --git a/src/openpower/state.py b/src/openpower/state.py index a3972ef1..1bc972fb 100644 --- a/src/openpower/state.py +++ b/src/openpower/state.py @@ -1,6 +1,6 @@ from nmutil.iocontrol import RecordObject from nmigen import Signal -from soc.sv.svstate import SVSTATERec +from openpower.sv.svstate import SVSTATERec class CoreState(RecordObject): diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 5df66ce1..d9fb43ac 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -17,7 +17,7 @@ Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578 import os, sys from collections import OrderedDict -from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, +from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, SV64P_PID_SIZE, SVP64RMFields, SVP64RM_EXTRA2_SPEC_SIZE, SVP64RM_EXTRA3_SPEC_SIZE, @@ -25,10 +25,10 @@ from soc.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE, SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE, SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE, SVP64RM_ELWIDTH_SIZE) -from soc.decoder.pseudo.pagereader import ISA -from soc.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra -from soc.decoder.selectable_int import SelectableInt -from soc.consts import SVP64MODE +from openpower.decoder.pseudo.pagereader import ISA +from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra +from openpower.decoder.selectable_int import SelectableInt +from openpower.consts import SVP64MODE # decode GPR into sv extra diff --git a/src/openpower/test/common.py b/src/openpower/test/common.py new file mode 100644 index 00000000..435cbc9a --- /dev/null +++ b/src/openpower/test/common.py @@ -0,0 +1,138 @@ +""" +Bugreports: +* https://bugs.libre-soc.org/show_bug.cgi?id=361 +""" + +import inspect +import functools +import types + + +# TODO: make this a util routine (somewhere) +def mask_extend(x, nbits, repeat): + res = 0 + extended = (1<