From f042559e9dbcc0738c6404903ac22da63cd27404 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 7 Jan 2019 10:07:28 +0100
Subject: [PATCH] Fix typo in manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 manual/CHAPTER_CellLib.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index d40a600ed..e22664a82 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -437,7 +437,7 @@ otherwise.
 \begin{lstlisting}[mathescape,language=Verilog]
 	always @($ClkEdge$ C, $RstEdge$ R)
 		if (R == $RstLvl$)
-			Q <= $RstVa$l;
+			Q <= $RstVal$;
 		else
 			Q <= D;
 \end{lstlisting}
-- 
2.30.2