From f06af8c8082b74c0dca372c05273f422bf3c65d1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 17 Mar 2021 22:25:21 +0000 Subject: [PATCH] add ascii graphic for extsw svp64 operation --- src/soc/decoder/isa/test_caller_svp64_predication.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py index de8e39bc..cd4df1e9 100644 --- a/src/soc/decoder/isa/test_caller_svp64_predication.py +++ b/src/soc/decoder/isa/test_caller_svp64_predication.py @@ -49,10 +49,20 @@ class DecoderTestCase(FHDLTestCase): # - dests are 5 and 6 # - source mask says "pick first element from source (5) # - dest mask says "pick *second* element from dest (10) + # # therefore the operation that's carried out is: # GPR(10) = extsb(GPR(5)) + # # this is a type of back-to-back VGATHER and VSCATTER but it applies # to *operations*, not just MVs like in traditional Vector ISAs + # ascii graphic: + # + # reg num 0 1 2 3 4 5 6 7 8 9 10 + # src ~r3=0b01 Y N + # | + # +-----+ + # | + # dest r3=0b10 N Y isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v' ]) -- 2.30.2