From f07b18a1b87f78a3463f98c318a848cc90806bbd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 24 Jul 2019 11:13:19 +0100 Subject: [PATCH] semi-working after "hack" to reduce LHS of algorithm by fract_width --- src/ieee754/fpcommon/test/fpmux.py | 1 + src/ieee754/fpdiv/div0.py | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py index 4d2a3b26..ef0a2f33 100644 --- a/src/ieee754/fpcommon/test/fpmux.py +++ b/src/ieee754/fpcommon/test/fpmux.py @@ -170,6 +170,7 @@ def create_random(num_rows, width, single_op=False, n_vals=10): #op1 = 0x4400 #op1 = 0x4800 #op1 = 0x48f0 + #op1 = 0x429 vals.append((op1,)) else: diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index d09e80e0..0c9ed334 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -118,11 +118,11 @@ class FPDivStage0Mod(Elaboratable): with m.Elif(self.i.ctx.op == 2): am0 = Signal(len(self.i.a.m)+3, reset_less=True) with m.If(self.i.a.e[0]): - m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-2)) - m.d.comb += self.o.z.e.eq(-((self.i.a.e+1) >> 1)+1) + m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-3)) + m.d.comb += self.o.z.e.eq(-((self.i.a.e+1) >> 1)+4) with m.Else(): - m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-2)) - m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+1) + m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-3)) + m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+2) m.d.comb += [self.o.z.s.eq(self.i.a.s), self.o.divisor_radicand.eq(am0), -- 2.30.2