From f0ab28c706505e7d91cd030ee157d2324c1ec701 Mon Sep 17 00:00:00 2001 From: Shriya Sharma Date: Wed, 27 Sep 2023 08:43:17 +0100 Subject: [PATCH] Added english language description and brackets for lmw instruction --- openpower/isa/fixedload.mdwn | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn index 233b45ed..bcde4ec0 100644 --- a/openpower/isa/fixedload.mdwn +++ b/openpower/isa/fixedload.mdwn @@ -744,7 +744,7 @@ Special Registers Altered: # Load Multiple Word -DQ-Form +D-Form * lmw RT,D(RA) @@ -758,6 +758,22 @@ Pseudo-code: r <- r + 1 EA <- EA + 4 +Description: + + Let n = (32-RT). Let the effective address (EA) be the + sum (RA|0)+ D. + + n consecutive words starting at EA are loaded into the + low-order 32 bits of GPRs RT through 31. The + high-order 32 bits of these GPRs are set to zero. + + If RA is in the range of registers to be loaded, including + the case in which RA=0, the instruction form is invalid. + + This instruction is not supported in Little-Endian mode. + If it is executed in Little-Endian mode, the system align- + ment error handler is invoked. + Special Registers Altered: None -- 2.30.2