From f1022c90ad7f6b94257c1b2fda3b46a5db9c9867 Mon Sep 17 00:00:00 2001 From: Paul Brook Date: Wed, 26 Oct 2005 14:09:29 +0000 Subject: [PATCH] 2005-10-26 Paul Brook gas/ * config/tc-arm.c (insns): Correct "sel" entry. gas/testsuite/ * gas/arm/archv6.d: Adjust expected output. opcodes/ * arm-dis.c (arm_opcodes): Correct "sel" entry. --- gas/ChangeLog | 4 ++++ gas/config/tc-arm.c | 2 +- gas/testsuite/ChangeLog | 4 ++++ gas/testsuite/gas/arm/archv6.d | 4 ++-- opcodes/ChangeLog | 4 ++++ opcodes/arm-dis.c | 2 +- 6 files changed, 16 insertions(+), 4 deletions(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index a68c0d87100..014622f1b13 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2005-10-26 Paul Brook + + * config/tc-arm.c (insns): Correct "sel" entry. + 2005-10-26 Jan Beulich * config/tc-i386.c (i386_operand): Don't check register prefix here. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index ed9632ca6f1..2f090b555f1 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -8928,7 +8928,7 @@ static const struct asm_opcode insns[] = TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah), TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth), - TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), + TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd), TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla), TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal), diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 0d297529f77..127e6a76eb1 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2005-10-26 Paul Brook + + * gas/arm/archv6.d: Adjust expected output. + 2005-10-26 Jan Beulich * gas/i386/intel.s: Replace register used in offset expression. diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d index 8bb7703d1a1..1dbaad3a714 100644 --- a/gas/testsuite/gas/arm/archv6.d +++ b/gas/testsuite/gas/arm/archv6.d @@ -64,8 +64,8 @@ Disassembly of section .text: 0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8 0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7 0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7 -0+0ec <[^>]*> e68210b3 ? sel r1, r2, r3 -0+0f0 <[^>]*> 168210b3 ? selne r1, r2, r3 +0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3 +0+0f0 <[^>]*> 16821fb3 ? selne r1, r2, r3 0+0f4 <[^>]*> f1010200 ? setend be 0+0f8 <[^>]*> f1010000 ? setend le 0+0fc <[^>]*> e6342f17 ? shadd16 r2, r4, r7 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 42c6fe9bf47..46175ce9bd4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2005-10-26 Paul Brook + + * arm-dis.c (arm_opcodes): Correct "sel" entry. + 2005-10-26 Kazuhiro Inaoka * m32r-asm.c: Regenerate. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index e5c3742b15a..236a1c9e3ad 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -557,7 +557,7 @@ static const struct opcode32 arm_opcodes[] = {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, - {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, + {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, -- 2.30.2