From f108770a8969f0a41463437208a62f9044810c49 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 15 May 2017 21:04:35 +0200 Subject: [PATCH] i386.i386.md (*zero_extendsidi2): Do not penalize non-interunit SSE move alternatives with '?'. * config/i386.i386.md (*zero_extendsidi2): Do not penalize non-interunit SSE move alternatives with '?'. (zero-extendsidi peephole2): New peephole to skip intermediate general register in SSE zero-extend sequence. testsuite/ChangeLog: * gcc.target/i386/pr80425-1.c: New test. * gcc.target/i386/pr80425-2.c: Ditto. From-SVN: r248070 --- gcc/ChangeLog | 7 +++++++ gcc/config/i386/i386.md | 13 +++++++++++-- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/gcc.target/i386/pr80425-1.c | 12 ++++++++++++ gcc/testsuite/gcc.target/i386/pr80425-2.c | 14 ++++++++++++++ 5 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr80425-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr80425-2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 18b6ed59c73..3d5cc12b970 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-05-15 Uros Bizjak + + * config/i386.i386.md (*zero_extendsidi2): Do not penalize + non-interunit SSE move alternatives with '?'. + (zero-extendsidi peephole2): New peephole to skip intermediate + general register in SSE zero-extend sequence. + 2017-05-15 Jeff Law * reorg.c (relax_delay_slots): Create a new variable to hold diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index da79d8fe1b8..6aca64b59be 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3762,10 +3762,10 @@ (define_insn "*zero_extendsidi2" [(set (match_operand:DI 0 "nonimmediate_operand" - "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?r,?*Yi,?*x,?*x,?*v,*r") + "=r,?r,?o,r ,o,?*Ym,?!*y,?r ,?r,?*Yi,*x,*x,*v,*r") (zero_extend:DI (match_operand:SI 1 "x86_64_zext_operand" - "0 ,rm,r ,rmWz,0,r ,m ,*Yj,*x,r ,m , *x, *v,*k")))] + "0 ,rm,r ,rmWz,0,r ,m ,*Yj,*x,r ,m ,*x,*v,*k")))] "" { switch (get_attr_type (insn)) @@ -3885,6 +3885,15 @@ (set (match_dup 4) (const_int 0))] "split_double_mode (DImode, &operands[0], 1, &operands[3], &operands[4]);") +(define_peephole2 + [(set (match_operand:DI 0 "general_reg_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand"))) + (set (match_operand:DI 2 "sse_reg_operand") (match_dup 0))] + "TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC + && peep2_reg_dead_p (2, operands[0])" + [(set (match_dup 2) + (zero_extend:DI (match_dup 1)))]) + (define_mode_attr kmov_isa [(QI "avx512dq") (HI "avx512f") (SI "avx512bw") (DI "avx512bw")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9fb8c8598b8..2436fa888e0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2017-05-15 Uros Bizjak + + * gcc.target/i386/pr80425-1.c: New test. + * gcc.target/i386/pr80425-2.c: Ditto. + 2017-05-15 Jeff Law * gcc.target/mips/reorgbug-1.c: New test. diff --git a/gcc/testsuite/gcc.target/i386/pr80425-1.c b/gcc/testsuite/gcc.target/i386/pr80425-1.c new file mode 100644 index 00000000000..5b2841e8c87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80425-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=intel" } */ + +#include + +__m512i +f1 (__m512i x, int a) +{ + return _mm512_srai_epi32 (x, a); +} + +/* { dg-final { scan-assembler-times "movd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr80425-2.c b/gcc/testsuite/gcc.target/i386/pr80425-2.c new file mode 100644 index 00000000000..e6b15ef9a9e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80425-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -mtune=intel" } */ + +#include + +extern int a; + +__m512i +f1 (__m512i x) +{ + return _mm512_srai_epi32 (x, a); +} + +/* { dg-final { scan-assembler-times "movd\[ \\t\]+\[^\n\]*%xmm" 1 } } */ -- 2.30.2