From f112b90b2af259bc42d9fbf8ad684bd92a837a4b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Oct 2018 14:10:13 +0000
Subject: [PATCH] morph conversion of floating-point for storing, through
 sv_proc_t

---
 riscv/insns/c_fsd.h       |  2 +-
 riscv/insns/c_fsdsp.h     |  2 +-
 riscv/insns/c_fsw.h       |  2 +-
 riscv/insns/c_fswsp.h     |  2 +-
 riscv/insns/fmv_x_d.h     |  2 +-
 riscv/insns/fmv_x_w.h     |  2 +-
 riscv/insns/fsd.h         |  2 +-
 riscv/insns/fsw.h         |  2 +-
 riscv/sv_insn_redirect.cc | 19 +++++++++++++++++++
 riscv/sv_insn_redirect.h  |  4 ++++
 10 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index 421caa8..00c0b5d 100644
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_FRS2S.to_uint64()); // RVC_RS1S
+MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), to_uint64(RVC_FRS2S)); // RVC_RS1S
diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index e0b523e..2c12e59 100644
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_FRS2.to_uint64());
+MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), to_uint64(RVC_FRS2));
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 6cdd419..f8f460c 100644
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), RVC_FRS2S.to_uint32()); //RVC_RS1S
+  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), to_uint32(RVC_FRS2S)); //RVC_RS1S
 } else { // c.sd
   MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_RS2S); //RVC_RS1S, 
 }
diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index 2da9618..a8e5eec 100644
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), RVC_FRS2.to_uint32());
+  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), to_uint32(RVC_FRS2));
 } else { // c.sdsp
   MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_RS2);
 }
diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index 1dd2511..f6719e6 100644
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(FRS1.to_uint64());
+WRITE_RD(to_uint64(FRS1));
diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index 616c7e9..6247c6c 100644
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(sv_reg_t(FRS1.to_uint32())));
+WRITE_RD(sext32(to_uint32(FRS1)));
diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 40b5b73..c7cf869 100644
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rs1(), insn.s_imm(), FRS2.to_uint64()); // RS1
+MMU.store_uint64(insn.rs1(), insn.s_imm(), to_uint64(FRS2)); // RS1
diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 0b70997..054bd4d 100644
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(insn.rs1(), insn.s_imm(), FRS2.to_uint32()); // RS1
+MMU.store_uint32(insn.rs1(), insn.s_imm(), to_uint32(FRS2)); // RS1
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 0327fb6..ce3db5f 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -885,6 +885,25 @@ void sv_proc_t::mmu_store(reg_spec_t const& spec, sv_reg_t const& offs,
     }
 }
 
+// ------
+
+sv_reg_t sv_proc_t::to_uint64(sv_freg_t const& reg)
+{
+    return sv_reg_t(reg.to_uint64());
+}
+
+sv_reg_t sv_proc_t::to_uint32(sv_freg_t const& reg)
+{
+    return sv_reg_t(reg.to_uint32());
+}
+
+sv_reg_t sv_proc_t::to_uint32(sv_float32_t const& reg)
+{
+    return sv_reg_t(reg.to_uint32());
+}
+
+// ------
+
 uint64_t sv_freg_t::to_uint64() const&
 {
     return reg.v[0];
diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 6314c4c..839ae02 100644
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -252,6 +252,10 @@ public:
                    size_t width, reg_t val);
 
 
+    sv_reg_t to_uint64(sv_freg_t const& reg);
+    sv_reg_t to_uint32(sv_freg_t const& reg);
+    sv_reg_t to_uint32(sv_float32_t const& reg);
+
 #include "sv_insn_decl.h"
 };
 
-- 
2.30.2