From f13f5f5e690d699337610443c552d5387b2a7528 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Sun, 18 Sep 2022 18:32:33 +0300 Subject: [PATCH] power_insn: support RC1/~RC1 in ff/pr --- src/openpower/decoder/power_insn.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 96077e14..97a42196 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1399,6 +1399,13 @@ class NormalFailFirstRc0RM(NormalBaseRM): VLi: BaseRM.mode[3] RC1: BaseRM.mode[4] + def specifiers(self, record): + if self.RC1: + inv = "~" if self.inv else "" + yield f"ff={inv}RC1" + + yield from super().specifiers(record=record) + class NormalSaturationRM(NormalBaseRM): """normal: sat mode: N=0/1 u/s, SUBVL=1""" @@ -1436,6 +1443,9 @@ class NormalPredResultRc0RM(NormalBaseRM): def specifiers(self, record): if self.zz: yield f"zz" + if self.RC1: + inv = "~" if self.inv else "" + yield f"pr={inv}RC1" yield from super().specifiers(record=record) @@ -1486,6 +1496,12 @@ class LDSTImmFailFirstRc0RM(LDSTImmBaseRM): els: BaseRM.mode[3] RC1: BaseRM.mode[4] + def specifiers(self, record): + if self.RC1: + inv = "~" if self.inv else "" + yield f"ff={inv}RC1" + + yield from super().specifiers(record=record) class LDSTImmSaturationRM(LDSTImmBaseRM): """ld/st immediate: sat mode: N=0/1 u/s""" @@ -1518,6 +1534,12 @@ class LDSTImmPredResultRc0RM(LDSTImmBaseRM): els: BaseRM.mode[3] RC1: BaseRM.mode[4] + def specifiers(self, record): + if self.RC1: + inv = "~" if self.inv else "" + yield f"pr={inv}RC1" + + yield from super().specifiers(record=record) class LDSTImmRM(LDSTImmBaseRM): simple: LDSTImmSimpleRM @@ -1599,6 +1621,9 @@ class LDSTIdxPredResultRc0RM(LDSTIdxBaseRM): def specifiers(self, record): if self.zz: yield f"zz" + if self.RC1: + inv = "~" if self.inv else "" + yield f"pr={inv}RC1" yield from super().specifiers(record=record) -- 2.30.2