From f144adec587e2d0e993098abc5b576721ba969dd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 21 Dec 2016 10:16:47 +0100 Subject: [PATCH] Added AIGER back-end to automatic back-end detection --- kernel/yosys.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 08fee9741..3d0aca78e 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig command = "verilog"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") command = "ilang"; + else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig") + command = "aiger"; else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif") command = "blif"; else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif") -- 2.30.2