From f148a434f6a8e22a3db9176cc787aa2fc8aac4c7 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Tue, 10 Jan 2012 10:06:11 +0100 Subject: [PATCH] constraints.md ("L"): Return true for 0xffffffff. * config/i386/constraints.md ("L"): Return true for 0xffffffff. * config/i386/i386.c (*anddi_1): Emit AND with 0xffffffff as MOV. From-SVN: r183054 --- gcc/ChangeLog | 13 +++++++++---- gcc/config/i386/constraints.md | 6 ++++-- gcc/config/i386/i386.md | 32 ++++++++++++++++++-------------- 3 files changed, 31 insertions(+), 20 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 28a8fa54199..290b976a767 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2012-01-10 Uros Bizjak + + * config/i386/constraints.md ("L"): Return true for 0xffffffff. + * config/i386/i386.c (*anddi_1): Emit AND with 0xffffffff as MOV. + 2012-01-10 Tom de Vries PR rtl-optimization/51271 @@ -6,7 +11,7 @@ 2012-01-10 Richard Henderson - * config/arm/arm.c (arm_vectorize_vec_perm_const_ok, + * config/arm/arm.c (arm_vectorize_vec_perm_const_ok, TARGET_VECTORIZE_VEC_PERM_CONST_OK, neon_split_vcombine, MAX_VECT_LEN, struct expand_vec_perm_d, arm_expand_vec_perm_1, arm_expand_vec_perm, arm_evpc_neon_vuzp, arm_evpc_neon_vzip, arm_evpc_neon_vrev, @@ -95,7 +100,8 @@ Andrew Pinski PR debug/51471 - * reorg.c (fill_slots_from_thread): Don't speculate frame-related insns. + * reorg.c (fill_slots_from_thread): Don't speculate + frame-related insns. 2012-01-09 Richard Sandiford @@ -215,8 +221,7 @@ 2012-01-06 Torvald Riegel PR rtl-optimization/51771 - * builtin-attrs.def (ATTR_RETURNS_TWICE, ATTR_TM_NOTHROW_RT_LIST): - New. + * builtin-attrs.def (ATTR_RETURNS_TWICE, ATTR_TM_NOTHROW_RT_LIST): New. * gtm-builtins.def (BUILT_IN_TM_START): Add returns-twice attrib. 2012-01-05 Eric Botcazou diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index 941f48aa6e6..c231779b90b 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -149,9 +149,11 @@ (match_test "IN_RANGE (ival, -128, 127)"))) (define_constraint "L" - "@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move." + "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF} + for AND as a zero-extending move." (and (match_code "const_int") - (match_test "ival == 0xFF || ival == 0xFFFF"))) + (match_test "ival == 0xff || ival == 0xffff + || ival == (HOST_WIDE_INT) 0xffffffff"))) (define_constraint "M" "0, 1, 2, or 3 (shifts for the @code{lea} instruction)." diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 47e7c6b33e5..beaf5327dfa 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -7678,19 +7678,23 @@ enum machine_mode mode; gcc_assert (CONST_INT_P (operands[2])); - if (INTVAL (operands[2]) == 0xff) - mode = QImode; + if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffffff) + mode = SImode; + else if (INTVAL (operands[2]) == 0xffff) + mode = HImode; else { - gcc_assert (INTVAL (operands[2]) == 0xffff); - mode = HImode; + gcc_assert (INTVAL (operands[2]) == 0xff); + mode = QImode; } operands[1] = gen_lowpart (mode, operands[1]); - if (mode == QImode) - return "movz{bl|x}\t{%1, %k0|%k0, %1}"; - else + if (mode == SImode) + return "mov{l}\t{%1, %k0|%k0, %1}"; + else if (mode == HImode) return "movz{wl|x}\t{%1, %k0|%k0, %1}"; + else + return "movz{bl|x}\t{%1, %k0|%k0, %1}"; } default: @@ -7726,19 +7730,19 @@ enum machine_mode mode; gcc_assert (CONST_INT_P (operands[2])); - if (INTVAL (operands[2]) == 0xff) - mode = QImode; + if (INTVAL (operands[2]) == 0xffff) + mode = HImode; else { - gcc_assert (INTVAL (operands[2]) == 0xffff); - mode = HImode; + gcc_assert (INTVAL (operands[2]) == 0xff); + mode = QImode; } operands[1] = gen_lowpart (mode, operands[1]); - if (mode == QImode) - return "movz{bl|x}\t{%1, %0|%0, %1}"; - else + if (mode == HImode) return "movz{wl|x}\t{%1, %0|%0, %1}"; + else + return "movz{bl|x}\t{%1, %0|%0, %1}"; } default: -- 2.30.2