From f14cdda815e3142bccea710b4e5de9eeb5f6c9c3 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Oct 2018 04:51:10 +0100
Subject: [PATCH] add rvc_swsp_imm sv overload, provides vector unit stride now

---
 riscv/insn_template_sv.cc | 15 +++++++++------
 riscv/sv_decode.h         |  2 ++
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 5396eaa..f349384 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -37,9 +37,12 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             xstr(INSN), INSNCODE, p->get_state()->prv,
             s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
-#if defined(INSN_TYPE_C_STACK_LD) || defined(INSN_TYPE_C_STACK_ST)
+#ifdef INSN_TYPE_C_STACK_LD
     sp = insn._remap(X_SP, true, src_offs);
 #endif
+#ifdef INSN_TYPE_C_STACK_ST
+    sp = insn._remap(X_SP, true, dest_offs);
+#endif
 #ifdef INSN_CATEGORY_TWINPREDICATION
 #ifdef INSN_TYPE_C_STACK_LD
     src_pred = insn.predicate(sp, SRC_PREDINT, zeroingsrc);
@@ -81,7 +84,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
     if (*dest_offs >= vlen) {
         break;
     }
-#ifdef INSN_C_LWSP
+#ifdef INSN_C_SWSP
         fprintf(stderr, "pre twin reg %s src %d dest %d pred %lx %lx\n",
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
 #endif
@@ -112,13 +115,13 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
             xstr(INSN), *src_offs, *dest_offs, src_pred, dest_pred);
     }
 #endif
-#ifdef INSN_C_LWSP
+#ifdef INSN_C_SWSP
     fprintf(stderr, "pre %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %d sp %lx\n",
+                      "vlen %d stop %d pred %lx rdv %lx v %d rvc2 %d sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
-                dest_pred & (1<<voffs), READ_REG(insn._rd()),
-                insn._rd(), insn.rvc_lwsp_imm(), READ_REG(sp));
+                dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2()),
+                insn._rvc_rs2(), insn.rvc_lwsp_imm(), READ_REG(sp));
 #endif
       #include INCLUDEFILE
 #ifdef DEST_PREDINT
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index c74065f..aa9f952 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -31,6 +31,8 @@ public:
   uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs);
   uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_lwsp_imm()); }
   uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_ldsp_imm()); }
+  uint64_t rvc_swsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_swsp_imm()); }
+  uint64_t rvc_sdsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_sdsp_imm()); }
   uint64_t rd () { return predicated(_rd (), *offs_rd, prd); }
   uint64_t rs1() { return predicated(_rs1(), *offs_rs1, prs1); }
   uint64_t rs2() { return predicated(_rs2(), *offs_rs2, prs2); }
-- 
2.30.2