From f162b858f22e66dd553973c1275fc7994fc615f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 24 Jul 2016 13:59:57 +0200 Subject: [PATCH] Added CellEdgesDatabase API --- Makefile | 4 +- kernel/celledges.cc | 88 +++++++++++++++++++++++++++++++++++ kernel/celledges.h | 63 +++++++++++++++++++++++++ passes/tests/test_cell.cc | 96 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 kernel/celledges.cc create mode 100644 kernel/celledges.h diff --git a/Makefile b/Makefile index 7ed68ef42..3431dee86 100644 --- a/Makefile +++ b/Makefile @@ -279,7 +279,9 @@ $(eval $(call add_include_file,passes/fsm/fsmdata.h)) $(eval $(call add_include_file,frontends/ast/ast.h)) $(eval $(call add_include_file,backends/ilang/ilang_backend.h)) -OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/cellaigs.o +OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o +OBJS += kernel/cellaigs.o kernel/celledges.o + kernel/log.o: CXXFLAGS += -DYOSYS_SRC='"$(YOSYS_SRC)"' kernel/yosys.o: CXXFLAGS += -DYOSYS_DATDIR='"$(DATDIR)"' diff --git a/kernel/celledges.cc b/kernel/celledges.cc new file mode 100644 index 000000000..b6786b116 --- /dev/null +++ b/kernel/celledges.cc @@ -0,0 +1,88 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/celledges.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void add_bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + IdString A = "\\A", Y = "\\Y"; + + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + int a_width = GetSize(cell->getPort(A)); + int y_width = GetSize(cell->getPort(Y)); + + for (int i = 0; i < y_width; i++) + { + if (i < a_width) + db->add_edge(cell, A, i, Y, i); + else if (is_signed && a_width > 0) + db->add_edge(cell, A, a_width-1, Y, i); + } +} + +void add_bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) +{ + IdString A = "\\A", B = "\\B", Y = "\\Y"; + + bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + int a_width = GetSize(cell->getPort(A)); + int b_width = GetSize(cell->getPort(B)); + int y_width = GetSize(cell->getPort(Y)); + + if (cell->type == "$and" && !is_signed) { + if (a_width > b_width) + a_width = b_width; + else + b_width = a_width; + } + + for (int i = 0; i < y_width; i++) + { + if (i < a_width) + db->add_edge(cell, A, i, Y, i); + else if (is_signed && a_width > 0) + db->add_edge(cell, A, a_width-1, Y, i); + + if (i < b_width) + db->add_edge(cell, B, i, Y, i); + else if (is_signed && b_width > 0) + db->add_edge(cell, B, b_width-1, Y, i); + } +} + +PRIVATE_NAMESPACE_END + +bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_cell(RTLIL::Cell *cell) +{ + if (cell->type.in("$not", "$pos")) { + add_bitwise_unary_op(this, cell); + return true; + } + + if (cell->type.in("$and", "$or", "$xor", "$xnor")) { + add_bitwise_binary_op(this, cell); + return true; + } + + return false; +} + diff --git a/kernel/celledges.h b/kernel/celledges.h new file mode 100644 index 000000000..fe863766c --- /dev/null +++ b/kernel/celledges.h @@ -0,0 +1,63 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef CELLEDGES_H +#define CELLEDGES_H + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +YOSYS_NAMESPACE_BEGIN + +struct AbstractCellEdgesDatabase +{ + virtual ~AbstractCellEdgesDatabase() { } + virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) = 0; + bool add_cell(RTLIL::Cell *cell); +}; + +struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase +{ + SigMap &sigmap; + dict> db; + FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } + + virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override { + SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); + SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); + db[from_sigbit].insert(to_sigbit); + } +}; + +struct RevCellEdgesDatabase : AbstractCellEdgesDatabase +{ + SigMap &sigmap; + dict> db; + RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } + + virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit) override { + SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); + SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); + db[to_sigbit].insert(from_sigbit); + } +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index abd56d10b..5a47634ac 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -21,6 +21,7 @@ #include "kernel/yosys.h" #include "kernel/satgen.h" #include "kernel/consteval.h" +#include "kernel/celledges.h" #include "kernel/macc.h" #include @@ -305,6 +306,90 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, cell->check(); } +static void run_edges_test(RTLIL::Design *design, bool verbose) +{ + Module *module = *design->modules().begin(); + Cell *cell = *module->cells().begin(); + + ezSatPtr ezptr; + ezSAT &ez = *ezptr.get(); + + SigMap sigmap(module); + SatGen satgen(&ez, &sigmap); + + FwdCellEdgesDatabase edges_db(sigmap); + edges_db.add_cell(cell); + + dict> satgen_db; + + satgen.setContext(&sigmap, "X:"); + satgen.importCell(cell); + + satgen.setContext(&sigmap, "Y:"); + satgen.importCell(cell); + + vector> input_db, output_db; + + for (auto &conn : cell->connections()) + { + SigSpec bits = sigmap(conn.second); + + satgen.setContext(&sigmap, "X:"); + std::vector xbits = satgen.importSigSpec(bits); + + satgen.setContext(&sigmap, "Y:"); + std::vector ybits = satgen.importSigSpec(bits); + + for (int i = 0; i < GetSize(bits); i++) + if (cell->input(conn.first)) + input_db.emplace_back(bits[i], xbits[i], ybits[i]); + else + output_db.emplace_back(bits[i], xbits[i], ybits[i]); + } + + if (verbose) + log("\nSAT solving for all edges:\n"); + + for (int i = 0; i < GetSize(input_db); i++) + { + SigBit inbit = std::get<0>(input_db[i]); + + if (verbose) + log(" Testing input signal %s:\n", log_signal(inbit)); + + vector xinbits, yinbits; + for (int k = 0; k < GetSize(input_db); k++) + if (k != i) { + xinbits.push_back(std::get<1>(input_db[k])); + yinbits.push_back(std::get<2>(input_db[k])); + } + + int xyinbit_ok = ez.vec_eq(xinbits, yinbits); + + for (int k = 0; k < GetSize(output_db); k++) + { + SigBit outbit = std::get<0>(output_db[k]); + int xoutbit = std::get<1>(output_db[k]); + int youtbit = std::get<2>(output_db[k]); + + bool is_edge = ez.solve(xyinbit_ok, ez.XOR(xoutbit, youtbit)); + + if (is_edge) + satgen_db[inbit].insert(outbit); + + if (verbose) { + bool is_ref_edge = edges_db.db.count(inbit) && edges_db.db.at(inbit).count(outbit); + log(" %c %s %s\n", is_edge ? 'x' : 'o', log_signal(outbit), is_edge == is_ref_edge ? "OK" : "ERROR"); + } + } + } + + if (satgen_db == edges_db.db) + log("PASS.\n"); + else + log_error("SAT-based edge table does not match the database!\n"); +} + static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::string uut_name, std::ofstream &vlog_file) { log("Eval testing:%c", verbose ? '\n' : ' '); @@ -590,6 +675,9 @@ struct TestCellPass : public Pass { log(" -noeval\n"); log(" do not check const-eval models\n"); log("\n"); + log(" -edges\n"); + log(" test cell edges db creator against sat-based implementation\n"); + log("\n"); log(" -v\n"); log(" print additional debug information to the console\n"); log("\n"); @@ -609,6 +697,7 @@ struct TestCellPass : public Pass { bool constmode = false; bool nosat = false; bool noeval = false; + bool edges = false; int argidx; for (argidx = 1; argidx < GetSize(args); argidx++) @@ -662,6 +751,10 @@ struct TestCellPass : public Pass { noeval = true; continue; } + if (args[argidx] == "-edges") { + edges = true; + continue; + } if (args[argidx] == "-v") { verbose = true; continue; @@ -801,6 +894,9 @@ struct TestCellPass : public Pass { create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv); if (!write_prefix.empty()) { Pass::call(design, stringf("write_ilang %s_%s_%05d.il", write_prefix.c_str(), cell_type.c_str()+1, i)); + } else if (edges) { + Pass::call(design, "dump gold"); + run_edges_test(design, verbose); } else { Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str())); if (!nosat) -- 2.30.2