From f166049e23ea94ab589b4327fc1013173cff8972 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 Jul 2020 17:52:44 +0100 Subject: [PATCH] rename spr1 to fast1 in trap data --- src/soc/fu/trap/pipe_data.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 3b336e2b..a43c214c 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -5,27 +5,27 @@ from soc.fu.trap.trap_input_record import CompTrapOpSubset class TrapInputData(IntegerData): regspec = [('INT', 'ra', '0:63'), # RA ('INT', 'rb', '0:63'), # RB/immediate - ('FAST', 'spr1', '0:63'), # SRR0 - ('FAST', 'spr2', '0:63'), # SRR1 + ('FAST', 'fast1', '0:63'), # SRR0 + ('FAST', 'fast2', '0:63'), # SRR1 ('FAST', 'cia', '0:63'), # Program counter (current) ('FAST', 'msr', '0:63')] # MSR def __init__(self, pspec): super().__init__(pspec, False) # convenience - self.srr0, self.srr1 = self.spr1, self.spr2 + self.srr0, self.srr1 = self.fast1, self.fast2 self.a, self.b = self.ra, self.rb class TrapOutputData(IntegerData): regspec = [('INT', 'o', '0:63'), # RA - ('FAST', 'spr1', '0:63'), # SRR0 SPR - ('FAST', 'spr2', '0:63'), # SRR1 SPR + ('FAST', 'fast1', '0:63'), # SRR0 SPR + ('FAST', 'fast2', '0:63'), # SRR1 SPR ('FAST', 'nia', '0:63'), # NIA (Next PC) ('FAST', 'msr', '0:63')] # MSR def __init__(self, pspec): super().__init__(pspec, True) # convenience - self.srr0, self.srr1 = self.spr1, self.spr2 + self.srr0, self.srr1 = self.fast1, self.fast2 -- 2.30.2