From f174cc0b87374bb69e2206856aa1eaf0b10a6167 Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 May 2022 12:51:23 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 5473fea11..cc7f4098f 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -486,14 +486,20 @@ and first requires some background on various research efforts and commercial designs. Once the context is clear, their synthesis can be proposed. These are: -* [ZOLC: Zero-Overhead Loop Control]() +* [ZOLC: Zero-Overhead Loop Control](https://ieeexplore.ieee.org/abstract/document/1692906/) * [OpenCAPI and Extra-V](https://dl.acm.org/doi/abs/10.14778/3137765.3137776) * [Snitch](https://arxiv.org/abs/2002.10143) - - **ZOLC: Zero-Overhead Loop Control** +The simplest longest commercially successful deployment of Zero-overhead looping +has been in Texas Instruments TMS320 DSPs. Up to fourteen sub-instructions +within the VLIW word may be repeatedly deployed on successive clock +cycles until a countdown reaches zero. This extraordinarily simple +concept needs no branches, no complex Register Hazard +Management because it is down to the programmer (or, the compiler), +to ensure data overlaps do not occur. + **OpenCAPI and Extra-V** **Snitch** -- 2.30.2