From f1e390cbc94c3b481fa28f4c8792d5158ddc8b24 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 17 Dec 2018 15:50:43 +0000 Subject: [PATCH] back.rtlil: update for Yosys master. --- nmigen/back/rtlil.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index 6737130..70b9596 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -451,9 +451,7 @@ class _RHSValueCompiler(_ValueCompiler): raise TypeError # :nocov: def _prepare_value_for_Slice(self, value): - # Uncomment after the following is merged: https://github.com/YosysHQ/yosys/pull/741 - # if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)): - if isinstance(value, ast.Signal): + if isinstance(value, (ast.Signal, ast.Slice, ast.Cat)): sigspec = self(value) else: sigspec = self.s.rtlil.wire(len(value)) -- 2.30.2