From f20620360b62b6ab4ad2c67d7537b430161ce957 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 13:02:22 +0100
Subject: [PATCH] whoops missed set up of temp variable bw

---
 src/ieee754/div_rem_sqrt_rsqrt/core.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index a6a65cc8..c4076266 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -224,6 +224,7 @@ class DivPipeCoreSetupStage(Elaboratable):
         self.core_config = core_config
         self.i = self.ispec()
         self.o = self.ospec()
+        bw = core_config.bit_width
         if core_config.supported == [DP.UDivRem]:
             self.compare_len = bw * 2
         else:
-- 
2.30.2