From f207376407e0b7049b76128ecff9d89a772bd0f8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 30 Jul 2019 11:50:01 +0100 Subject: [PATCH] add copyright / bugreport notice --- src/ieee754/fpdiv/div0.py | 6 +++++- src/ieee754/fpdiv/div2.py | 5 ++++- src/ieee754/fpdiv/pipeline.py | 10 ++++++++-- src/ieee754/fpdiv/specialcases.py | 12 +++++++++++- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py index e8920833..7a39d727 100644 --- a/src/ieee754/fpdiv/div0.py +++ b/src/ieee754/fpdiv/div0.py @@ -3,7 +3,11 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton Copyright (C) 2019 Jacob Lifshay -Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99 +Relevant bugreports: +* http://bugs.libre-riscv.org/show_bug.cgi?id=99 +* http://bugs.libre-riscv.org/show_bug.cgi?id=43 +* http://bugs.libre-riscv.org/show_bug.cgi?id=44 + """ from nmigen import Module, Signal, Cat, Elaboratable, Const, Mux diff --git a/src/ieee754/fpdiv/div2.py b/src/ieee754/fpdiv/div2.py index 9e90155f..5a26ace7 100644 --- a/src/ieee754/fpdiv/div2.py +++ b/src/ieee754/fpdiv/div2.py @@ -3,7 +3,10 @@ Copyright (C) 2019 Luke Kenneth Casson Leighton Copyright (C) 2019 Jacob Lifshay -Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99 +Relevant bugreports: +* http://bugs.libre-riscv.org/show_bug.cgi?id=99 +* http://bugs.libre-riscv.org/show_bug.cgi?id=43 +* http://bugs.libre-riscv.org/show_bug.cgi?id=44 """ from nmigen import Module, Signal, Elaboratable, Cat diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py index 499bd79c..c73d3814 100644 --- a/src/ieee754/fpdiv/pipeline.py +++ b/src/ieee754/fpdiv/pipeline.py @@ -1,6 +1,12 @@ -"""IEEE Floating Point Divider Pipeline +"""IEEE754 Floating Point Divider Pipeline -Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99 +Copyright (C) 2019 Luke Kenneth Casson Leighton +Copyright (C) 2019 Jacob Lifshay + +Relevant bugreports: +* http://bugs.libre-riscv.org/show_bug.cgi?id=99 +* http://bugs.libre-riscv.org/show_bug.cgi?id=43 +* http://bugs.libre-riscv.org/show_bug.cgi?id=44 Stack looks like this: diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py index 75721de2..e0c9b078 100644 --- a/src/ieee754/fpdiv/specialcases.py +++ b/src/ieee754/fpdiv/specialcases.py @@ -1,4 +1,13 @@ -# IEEE Floating Point Multiplier +""" IEEE Floating Point Divider + +Copyright (C) 2019 Luke Kenneth Casson Leighton +Copyright (C) 2019 Jacob Lifshay + +Relevant bugreports: +* http://bugs.libre-riscv.org/show_bug.cgi?id=99 +* http://bugs.libre-riscv.org/show_bug.cgi?id=43 +* http://bugs.libre-riscv.org/show_bug.cgi?id=44 +""" from nmigen import Module, Signal, Cat, Const, Elaboratable from nmigen.cli import main, verilog @@ -65,6 +74,7 @@ class FPDIVSpecialCasesMod(Elaboratable): m.d.comb += abinf.eq(a1.is_inf & b1.is_inf) with m.If(self.i.ctx.op == 0): # DIV + # if a is NaN or b is NaN return NaN with m.If(abnan): m.d.comb += self.o.out_do_z.eq(1) -- 2.30.2