From f21b697c6a4841229cccd142916c159fb1852f3b Mon Sep 17 00:00:00 2001 From: Phanikiran Harithas Date: Sun, 10 Jun 2018 14:03:04 +0530 Subject: [PATCH] arch-power: Define more special purpose registers, mtspr,mfspr instructions This patch defines more special purpose registers taking their count to 49. This also defines the mtspr and mfspr instructions to move the contents to and from the these special purpose registers. [ego@linux.vnet.ibm.com: Fixed conflicts in src/arch/power/isa/decoder.isa, src/arch/power/isa/operands.isa, src/arch/power/registers.hh] [kajoljain797@gmail.com: Fixed rfid, hrfid, mtmsr, mtmsrd instructions] NOTE: Perhaps can be folded into the previous patch which introduces CR, MSR, PTCR, etc. Change-Id: I4dd6ba8c710c4c522fadc685b60fb039dfd0a743 Signed-off-by: Phanikiran Harithas Signed-off-by: Venkatnarayan Kulkarni Signed-off-by: Kajol Jain --- src/arch/power/isa/bitfields.isa | 6 ++ src/arch/power/isa/decoder.isa | 174 ++++++++++++++++++++++++++++--- src/arch/power/isa/operands.isa | 41 ++++++++ src/arch/power/registers.hh | 44 +++++++- 4 files changed, 246 insertions(+), 19 deletions(-) diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa index 0b5f23f08..2f828a674 100644 --- a/src/arch/power/isa/bitfields.isa +++ b/src/arch/power/isa/bitfields.isa @@ -94,3 +94,9 @@ def bitfield U_FIELD <15:12>; // Field for specifying a bit in CR or FPSCR def bitfield BT <25:21>; + +// BHRB Field +def bitfield BHRB <20:11>; + +//L field for mtmsr and SLB move from entry VSID,ESID instructions. +def bitfield L <16>; diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index cd18fa9b5..c7e07264a 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -121,6 +121,40 @@ decode PO default Unknown::unknown() { format MiscOp { 150: isync({{ }}, [ IsSerializeAfter ]); + + 18: rfid({{ + uint32_t msr12=(bits(MSR,60)&bits(SRR1,12)) + |((bits(MSR,60)^0x01)&bits(MSR,12)); + MSR = insertBits(MSR,12,msr12); + uint32_t msr60=bits(MSR,60)&bits(SRR1,60); + MSR = insertBits(MSR,60,msr60); + if((bits(MSR,34,32)!=0x02)|(bits(SRR1,34,32)!=0x00)) + MSR = insertBits(MSR,34,32,bits(SRR1,34,32)); + MSR = insertBits(MSR,15,(bits(SRR1,15)|bits(SRR1,14))); + MSR = insertBits(MSR,5,(bits(SRR1,5)|bits(SRR1,14))); + MSR = insertBits(MSR,4,(bits(SRR1,4)|bits(SRR1,14))); + MSR = insertBits(MSR,63,61,bits(SRR1,63,61)); + MSR = insertBits(MSR,59,35,bits(SRR1,59,35)); + MSR = insertBits(MSR,31,bits(SRR1,31)); + MSR = insertBits(MSR,26,22,bits(SRR1,26,22)); + MSR = insertBits(MSR,14,13,bits(SRR1,14,13)); + MSR = insertBits(MSR,11,6,bits(SRR1,11,6)); + MSR = insertBits(MSR,3,0,bits(SRR1,3,0)); + NIA = SRR0 & -4ULL; + }}); + 274: hrfid({{ + if((bits(MSR,34,32)!=0x02)|(bits(HSRR1,34,32)!=0x00)) + MSR = insertBits(MSR,34,32,bits(HSRR1,34,32)); + MSR = insertBits(MSR,15,(bits(HSRR1,15)|bits(HSRR1,14))); + MSR = insertBits(MSR,5,(bits(HSRR1,5)|bits(HSRR1,14))); + MSR = insertBits(MSR,4,(bits(HSRR1,4)|bits(HSRR1,14))); + MSR = insertBits(MSR,63,35,bits(HSRR1,63,35)); + MSR = insertBits(MSR,31,bits(HSRR1,31)); + MSR = insertBits(MSR,26,22,bits(HSRR1,26,22)); + MSR = insertBits(MSR,14,6,bits(HSRR1,14,6)); + MSR = insertBits(MSR,3,0,bits(HSRR1,3,0)); + NIA = HSRR0 & -4ULL; + }}); } default: decode DX_XO { @@ -502,6 +536,129 @@ decode PO default Unknown::unknown() { }}); } + // Generic integer format instructions. + format IntOp { + 339: decode SPR { + 0x20: mfxer({{ Rt = XER; }}); + 0x100: mflr({{ Rt = LR; }}); + 0x120: mfctr({{ Rt = CTR; }}); + 0x188: mftb({{ Rt = TB; }}); + 0x220: mfdscr({{ Rt = DSCR; }}); + 0x240: mfdsisr({{ Rt = DSISR; }}); + 0x260: mfdar({{ Rt = DAR; }}); + 0x2C0: mfdec({{ Rt = DEC; }}); + 0x340: mfsrr0({{ Rt = SRR0; }}); + 0x360: mfsrr1({{ Rt = SRR1; }}); + 0x380: mfcfar({{ Rt = CFAR; }}); + 0x104: mfctrl({{ Rt = CTRL; }}); + 0x008: mfvrsave({{ Rt = VRSAVE; }}); + 0x1A8: mftbu({{ Rt = TBU; }}); + 0x3E8: mfpvr({{ Rt = PVR; }}); + 0x01C: mfppr({{ Rt = PPR; }}); + 0x05C: mfppr2({{ Rt =PPR32; }}); + 0x20E: mfptcr({{ Rt = PTCR; }}); + 0x208: mfsprg0({{Rt = SPRG0;}}); + 0x228: mfsprg1({{Rt = SPRG1;}}); + 0x248: mfsprg2({{Rt = SPRG2;}}); + 0x268: mfsprg3({{Rt = SPRG3;}}); + 0x3c9: mflpcr({{Rt = LPCR;}}); + 0x324: mffscr({{Rt = FSCR;}}); + 0x2fa: mfpsscr({{Rt = PSSCR;}}); + 0x3e9: mflpidr({{Rt = LPIDR;}}); + 0x3c5: mfhfscr({{Rt = HFSCR;}}); + 0x21f: mfhir0({{Rt = HIR0;}}); + 0x3aa: mfamor({{Rt = AMOR;}}); + 0x3a1: mfiamr({{Rt = IAMR;}}); + 0x369: mfhssr1({{Rt = HSRR1;}}); + 0x349: mfhssr0({{Rt = HSRR0;}}); + 0x2c9: mfhdec({{Rt = HDEC;}}); + 0x24a: mfpcr({{Rt = PCR;}}); + } + 467: decode SPR { + 0x20: mtxer({{ XER = Rs; }}); + 0x100: mtlr({{ LR = Rs; }}); + 0x120: mtctr({{ CTR = Rs; }}); + 0x390: mttbl({{ TBL = Rs; }}); + 0x220: mtdscr({{ DSCR = Rs; }}); + 0x240: mtdsisr({{ DSISR = Rs; }}); + 0x260: mtdar({{ DAR = Rs; }}); + 0x2C0: mtdec({{ DEC = Rs; }}); + 0x340: mtsrr0({{ SRR0 = Rs; }}); + 0x360: mtsrr1({{ SRR1 = Rs; }}); + 0x380: mtcfar({{ CFAR = Rs; }}); + 0x304: mtctrl({{ CTRL = Rs; }}); + 0x008: mtvrsave({{ VRSAVE = Rs; }}); + 0x1A8: mttbu({{ TBU = Rs; }}); + 0x01C: mtppr({{ PPR = Rs; }}); + 0x05C: mtppr32({{ PPR32 = Rs; }}); + 0x20E: mtptcr({{ PTCR = Rs; }}); + 0x208: mtsprg0({{SPRG0 = Rs;}}); + 0x228: mtsprg1({{SPRG1 = Rs;}}); + 0x248: mtsprg2({{SPRG2 = Rs;}}); + 0x268: mtsprg3({{SPRG3 = Rs;}}); + 0x3c9: mtlpcr({{LPCR = Rs;}}); + 0x324: mtfscr({{FSCR = Rs;}}); + 0x258: mtmmcra({{MMCRA = Rs;}}); + 0x378: mtmmcr0({{MMCR0 = Rs;}}); + 0x3d8: mtmmcr1({{MMCR1 = Rs;}}); + 0x238: mtmmcr2({{MMCR2 = Rs;}}); + 0x2fa: mtpsscr({{PSSCR = Rs;}}); + 0x3e9: mtlpidr({{LPIDR = Rs;}}); + 0x201: mtpidr({{PIDR = Rs;}}); + 0x3c5: mthfscr({{HFSCR = Rs;}}); + 0x27a: mtmmcrc({{MMCRC = Rs;}}); + 0x209: mthsprg0({{HSPRG0 = Rs;}}); + 0x21f: mthir0({{HIR0 = Rs;}}); + 0x3aa: mtamor({{AMOR = Rs;}}); + 0x3a1: mtiamr({{IAMR = Rs;}}); + 0x369: mthssr1({{HSRR1 = Rs;}}); + 0x349: mthssr0({{HSRR0 = Rs;}}); + 0x2c9: mthdec({{HDEC = Rs;}}); + 0x24a: mtpcr({{PCR = Rs;}}); + } + 83: mfmsr({{ Rt = MSR }}); + 178: mtmsrd({{ + if (L == 0 ) { + uint64_t val = bits(Rs, 34, 32); + + if(bits(MSR, 34, 32) != 0x2 || val != 0x0) { + MSR = insertBits(MSR, 34, 32, val); + } + + val = bits(Rs, 14); + + MSR = insertBits(MSR, 5, bits(Rs, 5) | val); + MSR = insertBits(MSR, 4, bits(Rs, 4) | val); + + MSR = insertBits(MSR, 63, 61, bits(Rs, 63, 61)); + MSR = insertBits(MSR, 59, 35, bits(Rs, 59, 35)); + MSR = insertBits(MSR, 31, 16, bits(Rs, 31, 16)); + MSR = insertBits(MSR, 14, 13, bits(Rs, 14, 13)); + MSR = insertBits(MSR, 11, 6, bits(Rs, 11, 6)); + MSR = insertBits(MSR, 3, 1, bits(Rs, 3, 1)); + } else { + MSR = insertBits(MSR, 15, bits(Rs, 15)); + MSR = insertBits(MSR, 1, bits(Rs, 1)); + } + }}, [ IsPrivileged ]); + + 146: mtmsr({{ + if( L ==0 ){ + MSR = insertBits(MSR,15,bits(Rs,15)|bits(Rs,14)); + MSR = insertBits(MSR,5,bits(Rs,5)|bits(Rs,14)); + MSR = insertBits(MSR,4,bits(Rs,4)|bits(Rs,14)); + MSR = insertBits(MSR,31,16,bits(Rs,31,16)); + MSR = insertBits(MSR,14,13,bits(Rs,14,13)); + MSR = insertBits(MSR,11,6,bits(Rs,11,6)); + MSR = insertBits(MSR,3,1,bits(Rs,3,1)); + } + else{ + MSR = insertBits(MSR,15,bits(Rs,15)); + MSR = insertBits(MSR,1,bits(Rs,1)); + } + }}); + } + // Integer logic instructions use source registers Rs and Rb, // with destination register Ra. format IntLogicOp { @@ -700,23 +857,6 @@ decode PO default Unknown::unknown() { true); } - // Generic integer format instructions. - format IntOp { - 339: decode SPR { - 0x20: mfxer({{ Rt = XER; }}); - 0x100: mflr({{ Rt = LR; }}); - 0x120: mfctr({{ Rt = CTR; }}); - 0x32f: mftar({{ Rt = TAR; }}); - 0x188: mftb({{ Rt = 0; }}); // FIXME - } - 467: decode SPR { - 0x20: mtxer({{ XER = Rs; }}); - 0x100: mtlr({{ LR = Rs; }}); - 0x120: mtctr({{ CTR = Rs; }}); - 0x32f: mttar({{ TAR = Rs; }}); - } - } - format StoreIndexOp { 663: stfsx({{ Mem_sf = Fs_sf; }}); 727: stfdx({{ Mem_df = Fs; }}); diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa index d45cc11a7..8234ebb28 100644 --- a/src/arch/power/isa/operands.isa +++ b/src/arch/power/isa/operands.isa @@ -69,9 +69,50 @@ def operands {{ 'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9), 'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9), 'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9), + 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9), + 'DSCR': ('IntReg', 'ud', 'INTREG_DSCR', 'IsInteger', 9), + 'DSISR': ('IntReg', 'uw', 'INTREG_DSISR', 'IsInteger', 9), + 'DAR': ('IntReg', 'ud', 'INTREG_DAR', 'IsInteger', 9), + 'DEC': ('IntReg', 'ud', 'INTREG_DEC', 'IsInteger', 9), + 'SRR0': ('IntReg', 'ud', 'INTREG_SRR0', 'IsInteger', 9), + 'SRR1': ('IntReg', 'ud', 'INTREG_SRR1', 'IsInteger', 9), + 'CFAR': ('IntReg', 'ud', 'INTREG_CFAR', 'IsInteger', 9), + 'CTRL': ('IntReg', 'uw', 'INTREG_CTRL', 'IsInteger', 9), + 'VRSAVE': ('IntReg', 'uw', 'INTREG_VRSAVE', 'IsInteger', 9), + 'TB': ('IntReg', 'ud', 'INTREG_TB', 'IsInteger', 9), + 'TBU': ('IntReg', 'uw', 'INTREG_TBU', 'IsInteger', 9), + 'TBL': ('IntReg', 'uw', 'INTREG_TBL', 'IsInteger', 9), + 'PVR': ('IntReg', 'uw', 'INTREG_PVR', 'IsInteger', 9), + 'PPR': ('IntReg', 'ud', 'INTREG_PPR', 'IsInteger', 9), + 'PPR32': ('IntReg', 'uw', 'INTREG_PPR32', 'IsInteger', 9), + 'PTCR': ('IntReg', 'ud', 'INTREG_PTCR', 'IsInteger', 9), + 'SPRG0': ('IntReg', 'ud', 'INTREG_SPRG0', 'IsInteger', 9), + 'SPRG1': ('IntReg', 'ud', 'INTREG_SPRG1', 'IsInteger', 9), + 'SPRG2': ('IntReg', 'ud', 'INTREG_SPRG2', 'IsInteger', 9), + 'SPRG3': ('IntReg', 'ud', 'INTREG_SPRG3', 'IsInteger', 9), + 'LPCR': ('IntReg', 'ud', 'INTREG_LPCR', 'IsInteger' , 9), + 'FSCR': ('IntReg', 'ud', 'INTREG_FSCR', 'IsInteger' , 9), + 'MMCRA': ('IntReg', 'ud', 'INTREG_MMCRA', 'IsInteger' , 9), + 'MMCR0': ('IntReg', 'ud', 'INTREG_MMCR0', 'IsInteger' , 9), + 'MMCR1': ('IntReg', 'ud', 'INTREG_MMCR1', 'IsInteger' , 9), + 'MMCR2': ('IntReg', 'ud', 'INTREG_MMCR2', 'IsInteger' , 9), + 'PSSCR': ('IntReg', 'ud', 'INTREG_PSSCR', 'IsInteger' , 9), + 'LPIDR': ('IntReg', 'uw', 'INTREG_LPIDR', 'IsInteger' , 9), + 'PIDR': ('IntReg', 'uw', 'INTREG_PIDR', 'IsInteger' , 9), + 'HFSCR': ('IntReg', 'ud', 'INTREG_HFSCR', 'IsInteger' , 9), + 'HSPRG0': ('IntReg', 'ud', 'INTREG_HSPRG0', 'IsInteger' , 9), + 'HIR0': ('IntReg', 'ud', 'INTREG_HIR0', 'IsInteger' , 9), + 'MMCRC': ('IntReg', 'ud', 'INTREG_MMCRC', 'IsInteger' , 9), + 'AMOR': ('IntReg', 'ud', 'INTREG_AMOR', 'IsInteger' , 9), + 'IAMR': ('IntReg', 'ud', 'INTREG_IAMR', 'IsInteger' , 9), + 'HSRR1': ('IntReg', 'ud', 'INTREG_HSRR1', 'IsInteger' , 9), + 'HSRR0': ('IntReg', 'ud', 'INTREG_HSRR0', 'IsInteger' , 9), + 'HDEC': ('IntReg', 'ud', 'INTREG_HDEC', 'IsInteger' , 9), + 'PCR': ('IntReg', 'ud', 'INTREG_PCR', 'IsInteger' , 9), # Setting as IntReg so things are stored as an integer, not double 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), + 'MSR': ('IntReg', 'ud', 'INTREG_MSR', 'IsFloating', 9), # Registers for linked loads and stores 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9), diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh index 20eae565b..84bf6a2a7 100644 --- a/src/arch/power/registers.hh +++ b/src/arch/power/registers.hh @@ -68,7 +68,7 @@ const int NumIntArchRegs = 32; // CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR // and zero register, which doesn't actually exist but needs a number -const int NumIntSpecialRegs = 10; +const int NumIntSpecialRegs = 49; const int NumFloatArchRegs = 32; const int NumFloatSpecialRegs = 0; const int NumInternalProcRegs = 0; @@ -110,7 +110,47 @@ enum MiscIntRegNums { INTREG_FPSCR, INTREG_RSV, INTREG_RSV_LEN, - INTREG_RSV_ADDR + INTREG_RSV_ADDR, + INTREG_DSCR, + INTREG_DSISR, + INTREG_DAR, + INTREG_DEC, + INTREG_SRR0, + INTREG_SRR1, + INTREG_CFAR, + INTREG_CTRL, + INTREG_VRSAVE, + INTREG_TB, + INTREG_TBL, + INTREG_TBU, + INTREG_PVR, + INTREG_PPR, + INTREG_PPR32, + INTREG_MSR, + INTREG_SPRG0, + INTREG_SPRG1, + INTREG_SPRG2, + INTREG_SPRG3, + INTREG_LPCR, + INTREG_PTCR, + INTREG_FSCR, + INTREG_MMCRA, + INTREG_MMCR0, + INTREG_MMCR1, + INTREG_MMCR2, + INTREG_PSSCR, + INTREG_LPIDR, + INTREG_PIDR, + INTREG_HFSCR, + INTREG_HSPRG0, + INTREG_HIR0, + INTREG_MMCRC, + INTREG_AMOR, + INTREG_IAMR, + INTREG_HSRR0, + INTREG_HSRR1, + INTREG_HDEC, + INTREG_PCR }; } // namespace PowerISA -- 2.30.2