From f22106e5ef001f4be51257ac22d8e5779b9d4c0e Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 20 Apr 2019 08:12:29 +0000 Subject: [PATCH] back.rtlil: allow record slices on LHS. --- nmigen/back/rtlil.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index b338491..fd3bfe8 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -4,7 +4,7 @@ from collections import defaultdict, OrderedDict from contextlib import contextmanager from ..tools import bits_for -from ..hdl import ast, ir, mem, xfrm +from ..hdl import ast, rec, ir, mem, xfrm __all__ = ["convert"] @@ -563,7 +563,7 @@ class _LHSValueCompiler(_ValueCompiler): return wire_next def _prepare_value_for_Slice(self, value): - assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat)) + assert isinstance(value, (ast.Signal, ast.Slice, ast.Cat, rec.Record)) return self(value) def on_Part(self, value): -- 2.30.2