From f2357f22dc48692756118a52b9ce3ae5171a07ca Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 23 Feb 2022 13:14:52 +0000 Subject: [PATCH] add comments about DRAM sync clock being identical to main clock --- src/crg.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/crg.py b/src/crg.py index 3cf483f..6fb8dd1 100644 --- a/src/crg.py +++ b/src/crg.py @@ -236,6 +236,8 @@ class ECPIX5CRG(Elaboratable): i_CLKI=ClockSignal("sync2x"), i_RST=0, o_CDIVX=ClockSignal("sync")) + + # temporarily set dram sync clock exactly equal to main sync m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync")) return m -- 2.30.2