From f24de88f385a3eeaadd9b9c8c200a7c338f37448 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 10 Jan 2020 17:13:27 -0800 Subject: [PATCH] log_debug() for abc9_{arrival,required} times --- backends/aiger/xaiger.cc | 8 ++++++++ passes/techmap/abc9_ops.cc | 8 +++++++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index cde53ff63..359d951b9 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -254,6 +254,14 @@ struct XAigerWriter log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); auto jt = arrivals.begin(); + +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + } +#endif + for (auto bit : sigmap(conn.second)) { arrival_times[bit] = *jt; if (arrivals.size() > 1) diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 918afd284..eac1ff2b6 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -512,7 +512,7 @@ void prep_times(RTLIL::Design *design) requireds.clear(); for (auto cell : boxes) { RTLIL::Module* inst_module = module->design->module(cell->type); - + log_assert(inst_module); for (auto &conn : cell->connections_) { auto port_wire = inst_module->wire(conn.first); if (!port_wire->port_input) @@ -537,6 +537,12 @@ void prep_times(RTLIL::Design *design) SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); for (const auto &i : requireds) { +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), i.first); + } +#endif delays.insert(i.first); for (auto offset : i.second) { auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); -- 2.30.2