From f27a0bc96739043c14d5fa0980955cd0536c4754 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 1 Oct 2020 18:16:27 +0100 Subject: [PATCH] revert bug in icache wishbone ack --- src/soc/experiment/icache.py | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 4788fda2..46ba5d0c 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -926,6 +926,18 @@ class ICache(Elaboratable): sync += r.wb.stb.eq(0) comb += stbs_done.eq(1) + # Calculate the next row address + rarange = Signal(LINE_OFF_BITS - ROW_OFF_BITS) + comb += rarange.eq( + r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1 + ) + sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq( + rarange + ) + sync += Display("RARANGE r.req_adr:%x rarange:%x " + "stbs_zero:%x stbs_done:%x", + r.req_adr, rarange, stbs_zero, stbs_done) + # Incoming acks processing with m.If(wb_in.ack): sync += Display("WB_IN_ACK data:%x stbs_zero:%x " @@ -956,20 +968,6 @@ class ICache(Elaboratable): # Increment store row counter sync += r.store_row.eq(next_row(r.store_row)) - # Calculate the next row address - rarange = Signal(LINE_OFF_BITS - ROW_OFF_BITS) - comb += rarange.eq( - r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS] + 1 - ) - sync += r.req_adr[ROW_OFF_BITS:LINE_OFF_BITS].eq( - rarange - ) - sync += Display("RARANGE r.req_adr:%x rarange:%x " - "stbs_zero:%x stbs_done:%x", - r.req_adr, rarange, - stbs_zero, stbs_done) - - # TLB miss and protection fault processing with m.If(flush_in | m_in.tlbld): sync += r.fetch_failed.eq(0) -- 2.30.2