From f28f2471303349e886b3636a0f55d7d533c3c084 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 21:30:19 +1000 Subject: [PATCH] soc: Don't create a wishbone slave to LiteDRAM with no CPU When creating a standalone LiteDRAM core with no CPU, there is no need to create a wishbone slave to LiteDRAM interface. Signed-off-by: Benjamin Herrenschmidt --- litex/soc/integration/soc.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 42366b6c..55bedb62 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1034,7 +1034,8 @@ class LiteXSoC(SoC): sdram_size = min(sdram_size, size) # Add SDRAM region - self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) + if self.cpu_type is not None: + self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) # SoC [<--> L2 Cache] <--> LiteDRAM -------------------------------------------------------- if len(self.cpu.memory_buses): @@ -1085,7 +1086,7 @@ class LiteXSoC(SoC): # Else raise Error. else: raise NotImplementedError - else: + elif self.cpu_type is not None: # When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM. # Request a LiteDRAM native port. -- 2.30.2