From f29f936e39ad4f6f797723752756b0dc8b497fda Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 4 Jul 2020 20:44:50 +0100
Subject: [PATCH] more updating spr1/spr2 to fast1/fast2

---
 src/soc/decoder/power_regspec_map.py              | 8 ++++----
 src/soc/fu/compunits/test/test_branch_compunit.py | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index a88375d0..2fc32fe0 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -88,9 +88,9 @@ def regspec_decode_read(e, regfile, name):
         if name == 'msr':
             return Const(1), MSR # TODO: detect read-conditions
         # TODO: remap the SPR numbers to FAST regs
-        if name == 'spr1':
+        if name == 'fast1':
             return e.read_fast1.ok, 1<<e.read_fast1.data
-        if name == 'spr2':
+        if name == 'fast2':
             return e.read_fast2.ok, 1<<e.read_fast2.data
 
     if regfile == 'SPR':
@@ -143,9 +143,9 @@ def regspec_decode_write(e, regfile, name):
         if name == 'msr':
             return None, MSR # hmmm
         # TODO: remap the SPR numbers to FAST regs
-        if name == 'spr1':
+        if name == 'fast1':
             return e.write_fast1, 1<<e.write_fast1.data
-        if name == 'spr2':
+        if name == 'fast2':
             return e.write_fast2, 1<<e.write_fast2.data
 
     if regfile == 'SPR':
diff --git a/src/soc/fu/compunits/test/test_branch_compunit.py b/src/soc/fu/compunits/test/test_branch_compunit.py
index dbcd0f65..622aabfd 100644
--- a/src/soc/fu/compunits/test/test_branch_compunit.py
+++ b/src/soc/fu/compunits/test/test_branch_compunit.py
@@ -42,16 +42,16 @@ class BranchTestRunner(TestRunner):
 
         # Link SPR
         lk = yield dec2.e.lk
-        branch_lk = 'spr2' in res
+        branch_lk = 'fast2' in res
         self.assertEqual(lk, branch_lk, code)
         if lk:
-            branch_lr = res['spr2']
+            branch_lr = res['fast2']
             self.assertEqual(sim.spr['LR'], branch_lr, code)
 
         # CTR SPR
-        ctr_ok = 'spr1' in res
+        ctr_ok = 'fast1' in res
         if ctr_ok:
-            ctr = res['spr1']
+            ctr = res['fast1']
             self.assertEqual(sim.spr['CTR'], ctr, code)
 
 
-- 
2.30.2