From f2a19f9980138744d2eabe5581bd4d0238193719 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 16 Feb 2022 01:23:13 +0000 Subject: [PATCH] * add uart_pins to UART16550 peripheral so they get connected * add yosys -abc9 option * correct path to external_core_top.v --- src/ls2.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index 43dd0d2..7d948f6 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -104,7 +104,7 @@ class DDR3SoC(SoC, Elaboratable): # UART at 0xC000_2000, convert 32-bit bus down to 8-bit in an odd way if uart_pins is not None: # sigh actual UART in microwatt is 8-bit - self.uart = UART16550(data_width=8) + self.uart = UART16550(data_width=8, pins=uart_pins) # but (see soc.vhdl) 8-bit regs are addressed at 32-bit locations cvtuartbus = wishbone.Interface(addr_width=5, data_width=32, granularity=8) @@ -210,8 +210,9 @@ class DDR3SoC(SoC, Elaboratable): # add the main core pth = os.path.split(__file__)[0] pth = os.path.join(pth, '../external_core_top.v') - with open(pth) as f: - platform.add_file('external_core_top.v', f) + fname = os.path.abspath(pth) + with open(fname) as f: + platform.add_file(fname, f) return m @@ -272,6 +273,10 @@ if __name__ == "__main__": uart_pins=uart_pins, firmware=firmware) + if toolchain == 'Trellis': + # add -abc9 option to yosys synth_ecp5 + os.environ['NMIGEN_synth_opts'] = '-abc9' + if platform is not None: # build and upload it platform.build(soc, do_program=True) -- 2.30.2