From f2a1daea5d49cfcbe0eca08db961d59e0a86b901 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Aug 2020 21:32:09 +0100 Subject: [PATCH] ha! "state" (pc, msr) not properly passed to core --- src/soc/simple/issuer.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index ae600054..05156119 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -66,9 +66,10 @@ class TestIssuer(Elaboratable): self.memerr_o = Signal(reset_less=True) # FAST regfile read /write ports for PC and MSR - self.state_r_pc = self.core.regs.rf['state'].r_ports['cia'] # PC rd - self.state_w_pc = self.core.regs.rf['state'].w_ports['d_wr1'] # PC wr - self.state_r_msr = self.core.regs.rf['state'].r_ports['msr'] # MSR rd + staterf = self.core.regs.rf['state'] + self.state_r_pc = staterf.r_ports['cia'] # PC rd + self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr + self.state_r_msr = staterf.r_ports['msr'] # MSR rd # DMI interface access intrf = self.core.regs.rf['int'] @@ -163,7 +164,7 @@ class TestIssuer(Elaboratable): dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode insn_type = core.e.do.insn_type - insn_state = pdecode2.state + dec_state = pdecode2.state # actually use a nmigen FSM for the first time (w00t) # this FSM is perhaps unusual in that it detects conditions @@ -206,10 +207,10 @@ class TestIssuer(Elaboratable): else: insn = f_instr_o.word_select(cur_state.pc[2], 32) comb += dec_opcode_i.eq(insn) # actual opcode + comb += dec_state.eq(cur_state) sync += core.e.eq(pdecode2.e) sync += ilatch.eq(insn) # latch current insn # also drop PC and MSR into decode "state" - sync += insn_state.eq(cur_state) m.next = "INSN_START" # move to "start" # waiting for instruction bus (stays there until not busy) -- 2.30.2