From f2dfce0470ccc644dbb34be02ad6f9f346012372 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 Aug 2020 15:29:01 +0100 Subject: [PATCH] investigating div fsm and simulator bug --- src/soc/decoder/selectable_int.py | 4 +++- src/soc/fu/compunits/compunits.py | 2 +- src/soc/fu/div/test/test_pipe_caller.py | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py index 700a6206..f98f6162 100644 --- a/src/soc/decoder/selectable_int.py +++ b/src/soc/decoder/selectable_int.py @@ -254,7 +254,9 @@ class SelectableInt: return SelectableInt(~self.value, self.bits) def __neg__(self): - return SelectableInt(~self.value + 1, self.bits) + res = SelectableInt((~self.value) + 1, self.bits) + print ("neg", hex(self.value), hex(res.value)) + return res def __lshift__(self, b): b = check_extsign(self, b) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 9a978b45..c4280fee 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -226,7 +226,7 @@ class AllFunctionUnits(Elaboratable): """ - def __init__(self, pspec, pilist=None, div_fsm=False): + def __init__(self, pspec, pilist=None, div_fsm=True): addrwid = pspec.addr_wid units = pspec.units if not isinstance(units, dict): diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py index ee8e5b95..4c8ee387 100644 --- a/src/soc/fu/div/test/test_pipe_caller.py +++ b/src/soc/fu/div/test/test_pipe_caller.py @@ -12,7 +12,7 @@ from soc.fu.div.test.helper import (log_rand, get_cu_inputs, class DivTestCases(TestAccumulatorBase): def case_divw_regression(self): - # simulator is wrong, FSM and power-instruction-analyzer are both correct + # simulator is wrong, FSM and power-instruction-analyzer both correct lst = [f"divw 0, 1, 2"] initial_regs = [0] * 32 initial_regs[2] = 0x2 -- 2.30.2