From f2f528e7811a56e5a9576661a99cd5978a9d563c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 27 Apr 2020 11:45:07 +0100 Subject: [PATCH] update text description to match diagram on L0 cache/buffer --- 3d_gpu/architecture/memory_and_cache.mdwn | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/3d_gpu/architecture/memory_and_cache.mdwn b/3d_gpu/architecture/memory_and_cache.mdwn index d3f5dd51f..da2caaf3e 100644 --- a/3d_gpu/architecture/memory_and_cache.mdwn +++ b/3d_gpu/architecture/memory_and_cache.mdwn @@ -15,13 +15,15 @@ Basic diagram: Cache/Buffers. Addr[4] determines which L0 Cache/Buffer to connect to. -* Twin L0 Cache/Buffers with only 16 128-bit-wide entries and +* A L0 Cache/Buffer with dual 8x 128-bit-wide entries and a single-clock, single-path outgoing read **or** write protocol, - with 16 (individual, non-multiplexed) incoming 128-bit entries. + with 8 pairs of (individual, non-multiplexed) incoming 128-bit entries + where each pair is hard-required to have the same top bits (12-48). + The left port has address bit 4 set to zero, the right port to 1. -* Each L0 Cache/Buffer connects by a single 128-bit data path +* The L0 Cache/Buffer connects to a pair of 128-bit data paths to a standard non-SMP-aware L1 cache. The data in and out - is again read **or** write, 128-bit-wide. + on each port is again read **or** write, 128-bit-wide. * A pair of Wishbone "funnels" take the 128-bit requests, which include byte-level access lines, and *if needed* create a pair of 64-bit -- 2.30.2