From f3072d498421280ed5b22f2bf016b4fbb4994cea Mon Sep 17 00:00:00 2001 From: =?utf8?q?J=C4=99drzej=20Boczar?= Date: Wed, 15 Jul 2020 15:47:06 +0200 Subject: [PATCH] soc/interconnect/axi: add connect methods for convenience --- litex/soc/interconnect/axi.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index d0886c1f..cb9c9ad8 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -55,6 +55,23 @@ def r_description(data_width, id_width): ("id", id_width) ] +def _connect_axi(master, slave): + channel_modes = { + "aw": "master", + "w" : "master", + "b" : "slave", + "ar": "master", + "r" : "slave", + } + r = [] + for channel, mode in channel_modes.items(): + if mode == "master": + m, s = getattr(master, channel), getattr(slave, channel) + else: + s, m = getattr(master, channel), getattr(slave, channel) + r.extend(m.connect(s)) + return r + class AXIInterface: def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"): self.data_width = data_width @@ -68,6 +85,9 @@ class AXIInterface: self.ar = stream.Endpoint(ax_description(address_width, id_width)) self.r = stream.Endpoint(r_description(data_width, id_width)) + def connect(self, slave): + return _connect_axi(self, slave) + # AXI Lite Definition ------------------------------------------------------------------------------ def ax_lite_description(address_width): @@ -138,6 +158,9 @@ class AXILiteInterface: r.append(pad.eq(sig)) return r + def connect(self, slave): + return _connect_axi(self, slave) + def write(self, addr, data, strb=None): if strb is None: strb = 2**len(self.w.strb) - 1 -- 2.30.2