From f31055a4efd4698af0728cca715d15b0b11737f6 Mon Sep 17 00:00:00 2001 From: "William D. Jones" Date: Tue, 1 Jan 2019 01:31:54 -0500 Subject: [PATCH] back.rtlil: Generate RTLIL for Assert/Assume statements. --- nmigen/back/rtlil.py | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py index fa75025..85856f8 100644 --- a/nmigen/back/rtlil.py +++ b/nmigen/back/rtlil.py @@ -565,6 +565,28 @@ class _StatementCompiler(xfrm.StatementVisitor): stmt.rhs, lhs_bits, lhs_sign) self._case.assign(self.lhs_compiler(stmt.lhs), rhs_sigspec) + def on_Assert(self, stmt): + self(stmt._check.eq(stmt.test)) + self(stmt._en.eq(1)) + + en_wire = self.rhs_compiler(stmt._en) + check_wire = self.rhs_compiler(stmt._check) + self.state.rtlil.cell("$assert", ports={ + "\\A": check_wire, + "\\EN": en_wire, + }, src=src(stmt.test.src_loc)) + + def on_Assume(self, stmt): + self(stmt._check.eq(stmt.test)) + self(stmt._en.eq(1)) + + en_wire = self.rhs_compiler(stmt._en) + check_wire = self.rhs_compiler(stmt._check) + self.state.rtlil.cell("$assume", ports={ + "\\A": check_wire, + "\\EN": en_wire, + }, src=src(stmt.test.src_loc)) + def on_Switch(self, stmt): self._check_rhs(stmt.test) -- 2.30.2