From f311ba7ed84d66ae2cd77bd969747d7ab959d866 Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Fri, 6 Jul 2018 16:18:19 +0100 Subject: [PATCH] Fix SBO bit in disassembly mask for ldrah on AArch64. The disassembly mask for ldarh incorrectly didn't mask out bit 20 which is part of the SBO part of the instruction and shouldn't be considered input. This fixes the wrong bit fixing the disassembly of instructions to ldarh and makes the behavior consistent. opcodes/ PR binutils/23242 * aarch64-tbl.h (ldarh): Fix disassembly mask. --- opcodes/ChangeLog | 5 +++++ opcodes/aarch64-tbl.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 70d35ebdaee..3b928875ebb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2018-07-06 Tamar Christina + + PR binutils/23242 + * aarch64-tbl.h (ldarh): Fix disassembly mask. + 2018-07-06 Tamar Christina PR binutils/23369 diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index c720fea511a..559efdba231 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3219,7 +3219,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), - CORE_INSN ("ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q), CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q), -- 2.30.2