From f333abcfcb5833ffe903fc778b111c7f7d031f1a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 9 May 2019 23:50:43 +0200 Subject: [PATCH] boards/targets: use new add_csr method --- litex/boards/targets/ac701.py | 13 +++---------- litex/boards/targets/arty.py | 14 ++++---------- litex/boards/targets/genesys2.py | 13 +++---------- litex/boards/targets/kc705.py | 13 +++---------- litex/boards/targets/kcu105.py | 13 +++---------- litex/boards/targets/nexys4ddr.py | 6 +----- litex/boards/targets/nexys_video.py | 13 +++---------- litex/boards/targets/simple.py | 8 ++------ litex/boards/targets/versa_ecp5.py | 13 +++---------- litex/tools/litex_sim.py | 21 +++++---------------- 10 files changed, 30 insertions(+), 97 deletions(-) diff --git a/litex/boards/targets/ac701.py b/litex/boards/targets/ac701.py index a10885d1..e37c456f 100755 --- a/litex/boards/targets/ac701.py +++ b/litex/boards/targets/ac701.py @@ -47,10 +47,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = ac701.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -62,6 +58,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, @@ -70,12 +67,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -88,6 +79,7 @@ class EthernetSoC(BaseSoC): if phy == "rgmii": self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) + self.add_csr("ethphy") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) @@ -128,6 +120,7 @@ class EthernetSoC(BaseSoC): interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 683b3024..e1feeda2 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -51,10 +51,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = arty.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -66,6 +62,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT41K128M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, @@ -74,12 +71,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -90,10 +81,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") @@ -105,6 +98,7 @@ class EthernetSoC(BaseSoC): self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) + # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index d529e0e3..7ae3d00b 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -42,10 +42,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = genesys2.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -57,6 +53,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT41J256M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, @@ -65,12 +62,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC ------------------------------------------------------------------------------------------ class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -81,10 +72,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 93b435a9..fa3d2fd9 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -42,10 +42,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kc705.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -57,6 +53,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, @@ -65,12 +62,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC ------------------------------------------------------------------------------------------ class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -81,10 +72,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 5105a399..264e0842 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -78,10 +78,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = kcu105.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -93,6 +89,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype="DDR4", sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) sdram_module = EDY4016A(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, @@ -103,12 +100,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC ------------------------------------------------------------------------------------------ class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -120,10 +111,12 @@ class EthernetSoC(BaseSoC): self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.cd_eth_rx.clk.attr.add("keep") diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 56df5182..c0b87fcf 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -16,7 +16,6 @@ from litedram.phy import s7ddrphy # CRG ---------------------------------------------------------------------------------------------- - class _CRG(Module): def __init__(self, platform, sys_clk_freq): self.clock_domains.cd_sys = ClockDomain() @@ -43,10 +42,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys4ddr.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -58,6 +53,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), memtype="DDR2", nphases=2, sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT47H64M16(sys_clk_freq, "1:2") self.register_sdram(self.ddrphy, sdram_module.geom_settings, diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index e82f1990..262fa7fe 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -46,10 +46,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(100e6), **kwargs): platform = nexys_video.Platform() SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -61,6 +57,7 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") sdram_module = MT41K256M16(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, @@ -69,12 +66,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -85,10 +76,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index f7832973..da67b66e 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -26,12 +26,6 @@ class BaseSoC(SoCCore): # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 20, - "ethmac": 21 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -42,10 +36,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 757b9e28..c7203777 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -73,10 +73,6 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - csr_map = { - "ddrphy": 16, - } - csr_map.update(SoCSDRAM.csr_map) def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, @@ -91,6 +87,7 @@ class BaseSoC(SoCSDRAM): self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") self.add_constant("ECP5DDRPHY", None) self.comb += crg.stop.eq(self.ddrphy.init.stop) sdram_module = MT41K64M16(sys_clk_freq, "1:2") @@ -101,12 +98,6 @@ class BaseSoC(SoCSDRAM): # EthernetSoC -------------------------------------------------------------------------------------- class EthernetSoC(BaseSoC): - csr_map = { - "ethphy": 18, - "ethmac": 19 - } - csr_map.update(BaseSoC.csr_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -118,10 +109,12 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) + self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") self.add_interrupt("ethmac") self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 8bae6b6b..126da466 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -84,22 +84,6 @@ class Platform(SimPlatform): class SimSoC(SoCSDRAM): - csr_peripherals = [ - "ethphy", - "ethmac", - - "etherbonephy", - "etherbonecore", - - "analyzer", - ] - csr_map_update(SoCSDRAM.csr_map, csr_peripherals) - - interrupt_map = { - "ethmac": 3, - } - interrupt_map.update(SoCSDRAM.interrupt_map) - mem_map = { "ethmac": 0x30000000, # (shadow @0xb0000000) } @@ -157,6 +141,7 @@ class SimSoC(SoCSDRAM): if with_ethernet: # eth phy self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) + self.add_csr("ethphy") # eth mac ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) @@ -165,11 +150,14 @@ class SimSoC(SoCSDRAM): self.submodules.ethmac = ethmac self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) + self.add_csr("ethmac") + self.add_interrupt("ethmac") # etherbone if with_etherbone: # eth phy self.submodules.etherbonephy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME + self.add_csr("etherbonephy") # eth core etherbonecore = LiteEthUDPIPCore(self.etherbonephy, etherbone_mac_address, convert_ip(etherbone_ip_address), sys_clk_freq) @@ -188,6 +176,7 @@ class SimSoC(SoCSDRAM): self.cpu.dbus ] self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512) + self.add_csr("analyzer") def main(): -- 2.30.2