From f33803a10fb7ea24eed14ce4e854f06b8409aa8d Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Thu, 19 Mar 2020 14:35:01 -0400 Subject: [PATCH] Add ld and st instructions to the reg/reg test --- src/soc/decoder/test/test_decoder_gas.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index 074e628f..9be815f5 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -28,6 +28,8 @@ class RegRegOp: "and": InternalOp.OP_AND, "or": InternalOp.OP_OR, "add.": InternalOp.OP_ADD, + "lwzx": InternalOp.OP_LOAD, + "stwx": InternalOp.OP_STORE, } self.opcodestr = random.choice(list(self.ops.keys())) self.opcode = self.ops[self.opcodestr] @@ -43,7 +45,11 @@ class RegRegOp: return string def check_results(self, pdecode2): - r1sel = yield pdecode2.e.write_reg.data + if self.opcode == InternalOp.OP_STORE: + r1sel = yield pdecode2.e.read_reg3.data + else: + r1sel = yield pdecode2.e.write_reg.data + r3sel = yield pdecode2.e.read_reg2.data # For some reason r2 gets decoded either in read_reg1 -- 2.30.2