From f33abd4eab08c0557a561b0fd4f16fc3d86433ab Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 16:44:11 -0700 Subject: [PATCH] Remove trailing space --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index b4657daca..6e8729256 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -269,7 +269,7 @@ endmodule module FDCE ( (* abc_arrival=303 *) output reg Q, - (* clkbuf_sink *) + (* clkbuf_sink *) input C, input CE, D, CLR ); @@ -289,7 +289,7 @@ endmodule module FDPE ( (* abc_arrival=303 *) output reg Q, - (* clkbuf_sink *) + (* clkbuf_sink *) input C, input CE, D, PRE ); -- 2.30.2