From f340bf7df1f95b71c996806801a6475fe1b15454 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 Aug 2020 00:25:36 +0100
Subject: [PATCH] divide alu pipeline into 2 (simple last)

---
 src/soc/fu/alu/pipeline.py              | 13 ++++++++++---
 src/soc/fu/alu/test/test_pipe_caller.py |  9 +++++++--
 2 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py
index a84efe1e..87ca1356 100644
--- a/src/soc/fu/alu/pipeline.py
+++ b/src/soc/fu/alu/pipeline.py
@@ -8,8 +8,13 @@ class ALUStages(PipeModBaseChain):
     def get_chain(self):
         inp = ALUInputStage(self.pspec)
         main = ALUMainStage(self.pspec)
+        return [inp, main]
+
+
+class ALUStageEnd(PipeModBaseChain):
+    def get_chain(self):
         out = ALUOutputStage(self.pspec)
-        return [inp, main, out]
+        return [out]
 
 
 class ALUBasePipe(ControlBase):
@@ -17,10 +22,12 @@ class ALUBasePipe(ControlBase):
         ControlBase.__init__(self)
         self.pspec = pspec
         self.pipe1 = ALUStages(pspec)
-        self._eqs = self.connect([self.pipe1])
+        self.pipe2 = ALUStageEnd(pspec)
+        self._eqs = self.connect([self.pipe1, self.pipe2])
 
     def elaborate(self, platform):
         m = ControlBase.elaborate(self, platform)
-        m.submodules.pipe = self.pipe1
+        m.submodules.pipe1 = self.pipe1
+        m.submodules.pipe2 = self.pipe2
         m.d.comb += self._eqs
         return m
diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index 842ce2db..aea6cb9d 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -187,7 +187,12 @@ class TestRunner(unittest.TestCase):
             fn_unit = yield pdecode2.e.do.fn_unit
             self.assertEqual(fn_unit, Function.ALU.value)
             yield from set_alu_inputs(alu, pdecode2, sim)
+
+            # set valid for one cycle, propagate through pipeline...
+            yield alu.p.valid_i.eq(1)
             yield
+            yield alu.p.valid_i.eq(0)
+
             opname = code.split(' ')[0]
             yield from sim.call(opname)
             index = sim.pc.CIA.value//4
@@ -199,6 +204,7 @@ class TestRunner(unittest.TestCase):
             yield
 
             yield from self.check_alu_outputs(alu, pdecode2, sim, code)
+            yield Settle()
 
     def test_it(self):
         test_data = ALUTestCase().test_data
@@ -214,8 +220,7 @@ class TestRunner(unittest.TestCase):
         m.submodules.alu = alu = ALUBasePipe(pspec)
 
         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
-        comb += alu.p.valid_i.eq(1)
-        comb += alu.n.ready_i.eq(1) # XXX ONLY works because ALU is 1 stage pipe
+        comb += alu.n.ready_i.eq(1)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
 
-- 
2.30.2