From f34c2d8d7041f803ceb8c1d035a57c569a52fa26 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 11 Apr 2022 09:18:57 +0100
Subject: [PATCH]

---
 openpower/sv/svp64/appendix.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 600e68de7..a94caed5e 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -738,7 +738,8 @@ illustration of normal mode add operation: zeroing not included, elwidth
 overrides not included.  if there is no predicate, it is set to all 1s
 
     function op_add(rd, rs1, rs2) # add not VADD!
-      int i, id=0, irs1=0, irs2=0; predval = get_pred_val(FALSE, rd);
+      int i, id=0, irs1=0, irs2=0;
+      predval = get_pred_val(FALSE, rd);
       for (i = 0; i < VL; i++)
         STATE.srcoffs = i # save context
         if (predval & 1<<i) # predication uses intregs
-- 
2.30.2