From f34c9c8af7ae6990d30a6a80dc2038039885b93f Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 21 May 2023 17:18:05 +0100 Subject: [PATCH] --- openpower/sv/ldst.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn index 926e3b625..a33ecf23c 100644 --- a/openpower/sv/ldst.mdwn +++ b/openpower/sv/ldst.mdwn @@ -93,10 +93,10 @@ of space, have the following quirks: Fields used in tables below: -* **sz / dz** if predication is enabled will put zeros into the dest +* **zz**: both sz and dz are set equal to this flag. + If predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero. otherwise the element is ignored or skipped, depending on context. -* **zz**: both sz and dz are set equal to this flag. * **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1) * **RC1** as if Rc=1, stores CRs *but not the result* @@ -177,7 +177,7 @@ but are the same `RM.MODE` bits (19:23 of `RM`): | 0 | 1 | 2 | 3 4 | description | |---|---| --- |---------|--------------------------- | -|els| 0 | SEA | dz sz | simple mode | +|els| 0 | PI | zz SEA | simple mode | |VLi| 1 | inv | CR-bit | ffirst CR sel | Vector Indexed Strided Mode is qualified as follows: -- 2.30.2