From f358462640beb7660b9ce2a31d5367fc33421ee1 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Mon, 6 Oct 2014 12:42:56 +0800 Subject: [PATCH] ilo: let shaders determine surface counts When a shader needs N surfaces, we should upload N surfaces and not depend on how many are bound. This commit is larger than it should be because we did not export how many surfaces a surface uses before. Signed-off-by: Chia-I Wu --- src/gallium/drivers/ilo/ilo_render_gen.h | 11 +- src/gallium/drivers/ilo/ilo_render_surface.c | 319 ++++++++---------- src/gallium/drivers/ilo/ilo_shader.c | 39 +++ src/gallium/drivers/ilo/ilo_shader.h | 11 + src/gallium/drivers/ilo/ilo_state.h | 12 +- .../drivers/ilo/shader/ilo_shader_fs.c | 33 +- .../drivers/ilo/shader/ilo_shader_gs.c | 8 +- .../drivers/ilo/shader/ilo_shader_internal.h | 14 + .../drivers/ilo/shader/ilo_shader_vs.c | 22 +- 9 files changed, 267 insertions(+), 202 deletions(-) diff --git a/src/gallium/drivers/ilo/ilo_render_gen.h b/src/gallium/drivers/ilo/ilo_render_gen.h index f21df4a5a2c..32d1237c18e 100644 --- a/src/gallium/drivers/ilo/ilo_render_gen.h +++ b/src/gallium/drivers/ilo/ilo_render_gen.h @@ -97,8 +97,7 @@ struct ilo_render { struct { uint32_t BINDING_TABLE_STATE; - int BINDING_TABLE_STATE_size; - uint32_t SURFACE_STATE[ILO_MAX_VS_SURFACES]; + uint32_t SURFACE_STATE[ILO_MAX_SURFACES]; uint32_t SAMPLER_STATE; uint32_t SAMPLER_BORDER_COLOR_STATE[ILO_MAX_SAMPLERS]; uint32_t PUSH_CONSTANT_BUFFER; @@ -107,15 +106,13 @@ struct ilo_render { struct { uint32_t BINDING_TABLE_STATE; - int BINDING_TABLE_STATE_size; - uint32_t SURFACE_STATE[ILO_MAX_GS_SURFACES]; + uint32_t SURFACE_STATE[ILO_MAX_SURFACES]; bool active; } gs; struct { uint32_t BINDING_TABLE_STATE; - int BINDING_TABLE_STATE_size; - uint32_t SURFACE_STATE[ILO_MAX_WM_SURFACES]; + uint32_t SURFACE_STATE[ILO_MAX_SURFACES]; uint32_t SAMPLER_STATE; uint32_t SAMPLER_BORDER_COLOR_STATE[ILO_MAX_SAMPLERS]; uint32_t PUSH_CONSTANT_BUFFER; @@ -153,8 +150,6 @@ struct ilo_render_draw_session { bool binding_table_vs_changed; bool binding_table_gs_changed; bool binding_table_fs_changed; - - int num_surfaces[PIPE_SHADER_TYPES]; }; struct ilo_render_rectlist_session { diff --git a/src/gallium/drivers/ilo/ilo_render_surface.c b/src/gallium/drivers/ilo/ilo_render_surface.c index c29aea1dfcd..22a7e488edf 100644 --- a/src/gallium/drivers/ilo/ilo_render_surface.c +++ b/src/gallium/drivers/ilo/ilo_render_surface.c @@ -38,46 +38,37 @@ gen6_emit_draw_surface_rt(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { + const struct ilo_shader_state *fs = vec->fs; + const struct ilo_fb_state *fb = &vec->fb; + uint32_t *surface_state; + int base, count, i; + ILO_DEV_ASSERT(r->dev, 6, 7.5); - /* SURFACE_STATEs for render targets */ - if (DIRTY(FB)) { - const struct ilo_fb_state *fb = &vec->fb; - const int offset = ILO_WM_DRAW_SURFACE(0); - uint32_t *surface_state = &r->state.wm.SURFACE_STATE[offset]; - int i; + if (!DIRTY(FS) && !DIRTY(FB)) + return; + if (!fs) + return; + + session->binding_table_fs_changed = true; - for (i = 0; i < fb->state.nr_cbufs; i++) { + base = ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_SURFACE_RT_BASE); + count = ilo_shader_get_kernel_param(fs, ILO_KERNEL_FS_SURFACE_RT_COUNT); + + /* SURFACE_STATEs for render targets */ + surface_state = &r->state.wm.SURFACE_STATE[base]; + for (i = 0; i < count; i++) { + if (i < fb->state.nr_cbufs && fb->state.cbufs[i]) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) fb->state.cbufs[i]; - if (!surface) { - surface_state[i] = - gen6_SURFACE_STATE(r->builder, &fb->null_rt, true); - } else { - assert(surface && surface->is_rt); - surface_state[i] = - gen6_SURFACE_STATE(r->builder, &surface->u.rt, true); - } - } - - /* - * Upload at least one render target, as - * brw_update_renderbuffer_surfaces() does. I don't know why. - */ - if (i == 0) { + assert(surface->is_rt); + surface_state[i] = + gen6_SURFACE_STATE(r->builder, &surface->u.rt, true); + } else { surface_state[i] = gen6_SURFACE_STATE(r->builder, &fb->null_rt, true); - - i++; } - - memset(&surface_state[i], 0, (ILO_MAX_DRAW_BUFFERS - i) * 4); - - if (i && session->num_surfaces[PIPE_SHADER_FRAGMENT] < offset + i) - session->num_surfaces[PIPE_SHADER_FRAGMENT] = offset + i; - - session->binding_table_fs_changed = true; } } @@ -86,38 +77,49 @@ gen6_emit_draw_surface_so(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { + const struct ilo_shader_state *vs = vec->vs; + const struct ilo_shader_state *gs = vec->gs; const struct ilo_so_state *so = &vec->so; + const struct pipe_stream_output_info *so_info; + uint32_t *surface_state; + int base, count, i; ILO_DEV_ASSERT(r->dev, 6, 6); - /* SURFACE_STATEs for stream output targets */ - if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) { - const struct pipe_stream_output_info *so_info = - (vec->gs) ? ilo_shader_get_kernel_so_info(vec->gs) : - (vec->vs) ? ilo_shader_get_kernel_so_info(vec->vs) : NULL; - const int offset = ILO_GS_SO_SURFACE(0); - uint32_t *surface_state = &r->state.gs.SURFACE_STATE[offset]; - int i; - - for (i = 0; so_info && i < so_info->num_outputs; i++) { - const int target = so_info->output[i].output_buffer; - const struct pipe_stream_output_target *so_target = - (target < so->count) ? so->states[target] : NULL; + if (!DIRTY(VS) && !DIRTY(GS) && !DIRTY(SO)) + return; - if (so_target) { - surface_state[i] = gen6_so_SURFACE_STATE(r->builder, - so_target, so_info, i); - } else { - surface_state[i] = 0; - } - } + if (gs) { + so_info = ilo_shader_get_kernel_so_info(gs); + base = ilo_shader_get_kernel_param(gs, + ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE); + count = ilo_shader_get_kernel_param(gs, + ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT); + } else if (vs) { + so_info = ilo_shader_get_kernel_so_info(vs); + base = 0; + count = ilo_shader_get_kernel_param(vs, + ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT); + } else { + return; + } - memset(&surface_state[i], 0, (ILO_MAX_SO_BINDINGS - i) * 4); + session->binding_table_gs_changed = true; - if (i && session->num_surfaces[PIPE_SHADER_GEOMETRY] < offset + i) - session->num_surfaces[PIPE_SHADER_GEOMETRY] = offset + i; + /* SURFACE_STATEs for stream output targets */ + surface_state = &r->state.gs.SURFACE_STATE[base]; + for (i = 0; i < count; i++) { + if (so_info && i < so_info->num_outputs && + so_info->output[i].output_buffer < so->count && + so->states[so_info->output[i].output_buffer]) { + const struct pipe_stream_output_target *so_target = + so->states[so_info->output[i].output_buffer]; - session->binding_table_gs_changed = true; + surface_state[i] = gen6_so_SURFACE_STATE(r->builder, + so_target, so_info, i); + } else { + surface_state[i] = 0; + } } } @@ -128,44 +130,45 @@ gen6_emit_draw_surface_view(struct ilo_render *r, struct ilo_render_draw_session *session) { const struct ilo_view_state *view = &vec->view[shader_type]; + const struct ilo_shader_state *sh; uint32_t *surface_state; - int offset, i; - bool skip = false; + int base, count, i; ILO_DEV_ASSERT(r->dev, 6, 7.5); - /* SURFACE_STATEs for sampler views */ switch (shader_type) { case PIPE_SHADER_VERTEX: - if (DIRTY(VIEW_VS)) { - offset = ILO_VS_TEXTURE_SURFACE(0); - surface_state = &r->state.vs.SURFACE_STATE[offset]; + if (!DIRTY(VS) && !DIRTY(VIEW_VS)) + return; + if (!vec->vs) + return; - session->binding_table_vs_changed = true; - } else { - skip = true; - } + sh = vec->vs; + surface_state = r->state.vs.SURFACE_STATE; + session->binding_table_vs_changed = true; break; case PIPE_SHADER_FRAGMENT: - if (DIRTY(VIEW_FS)) { - offset = ILO_WM_TEXTURE_SURFACE(0); - surface_state = &r->state.wm.SURFACE_STATE[offset]; + if (!DIRTY(FS) && !DIRTY(VIEW_FS)) + return; + if (!vec->fs) + return; - session->binding_table_fs_changed = true; - } else { - skip = true; - } + sh = vec->fs; + surface_state = r->state.wm.SURFACE_STATE; + session->binding_table_fs_changed = true; break; default: - skip = true; + return; break; } - if (skip) - return; + base = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_TEX_BASE); + count = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_TEX_COUNT); - for (i = 0; i < view->count; i++) { - if (view->states[i]) { + /* SURFACE_STATEs for sampler views */ + surface_state += base; + for (i = 0; i < count; i++) { + if (i < view->count && view->states[i]) { const struct ilo_view_cso *cso = (const struct ilo_view_cso *) view->states[i]; @@ -175,11 +178,6 @@ gen6_emit_draw_surface_view(struct ilo_render *r, surface_state[i] = 0; } } - - memset(&surface_state[i], 0, (ILO_MAX_SAMPLER_VIEWS - i) * 4); - - if (i && session->num_surfaces[shader_type] < offset + i) - session->num_surfaces[shader_type] = offset + i; } static void @@ -189,54 +187,53 @@ gen6_emit_draw_surface_const(struct ilo_render *r, struct ilo_render_draw_session *session) { const struct ilo_cbuf_state *cbuf = &vec->cbuf[shader_type]; + const struct ilo_shader_state *sh; uint32_t *surface_state; - bool *binding_table_changed; - int offset, count, i; + int base, count, i; ILO_DEV_ASSERT(r->dev, 6, 7.5); - if (!DIRTY(CBUF)) - return; - - /* SURFACE_STATEs for constant buffers */ switch (shader_type) { case PIPE_SHADER_VERTEX: - offset = ILO_VS_CONST_SURFACE(0); - surface_state = &r->state.vs.SURFACE_STATE[offset]; - binding_table_changed = &session->binding_table_vs_changed; + if (!DIRTY(VS) && !DIRTY(CBUF)) + return; + if (!vec->vs) + return; + + sh = vec->vs; + surface_state = r->state.vs.SURFACE_STATE; + session->binding_table_vs_changed = true; break; case PIPE_SHADER_FRAGMENT: - offset = ILO_WM_CONST_SURFACE(0); - surface_state = &r->state.wm.SURFACE_STATE[offset]; - binding_table_changed = &session->binding_table_fs_changed; + if (!DIRTY(FS) && !DIRTY(CBUF)) + return; + if (!vec->fs) + return; + + sh = vec->fs; + surface_state = r->state.wm.SURFACE_STATE; + session->binding_table_fs_changed = true; break; default: return; break; } - /* constants are pushed via PCB */ - if (cbuf->enabled_mask == 0x1 && !cbuf->cso[0].resource) { - memset(surface_state, 0, ILO_MAX_CONST_BUFFERS * 4); - return; - } + base = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_CONST_BASE); + count = ilo_shader_get_kernel_param(sh, ILO_KERNEL_SURFACE_CONST_COUNT); - count = util_last_bit(cbuf->enabled_mask); + /* SURFACE_STATEs for constant buffers */ + surface_state += base; for (i = 0; i < count; i++) { - if (cbuf->cso[i].resource) { + const struct ilo_cbuf_cso *cso = &cbuf->cso[i]; + + if (cso->resource) { surface_state[i] = gen6_SURFACE_STATE(r->builder, - &cbuf->cso[i].surface, false); + &cso->surface, false); } else { surface_state[i] = 0; } } - - memset(&surface_state[count], 0, (ILO_MAX_CONST_BUFFERS - count) * 4); - - if (count && session->num_surfaces[shader_type] < offset + count) - session->num_surfaces[shader_type] = offset + count; - - *binding_table_changed = true; } static void @@ -245,59 +242,55 @@ gen6_emit_draw_surface_binding_tables(struct ilo_render *r, int shader_type, struct ilo_render_draw_session *session) { - uint32_t *binding_table_state, *surface_state; - int *binding_table_state_size, size; - bool skip = false; + int count; ILO_DEV_ASSERT(r->dev, 6, 7.5); /* BINDING_TABLE_STATE */ switch (shader_type) { case PIPE_SHADER_VERTEX: - surface_state = r->state.vs.SURFACE_STATE; - binding_table_state = &r->state.vs.BINDING_TABLE_STATE; - binding_table_state_size = &r->state.vs.BINDING_TABLE_STATE_size; + if (!session->binding_table_vs_changed) + return; + if (!vec->vs) + return; + + count = ilo_shader_get_kernel_param(vec->vs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); - skip = !session->binding_table_vs_changed; + r->state.vs.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder, + r->state.vs.SURFACE_STATE, count); break; case PIPE_SHADER_GEOMETRY: - surface_state = r->state.gs.SURFACE_STATE; - binding_table_state = &r->state.gs.BINDING_TABLE_STATE; - binding_table_state_size = &r->state.gs.BINDING_TABLE_STATE_size; + if (!session->binding_table_gs_changed) + return; + if (vec->gs) { + count = ilo_shader_get_kernel_param(vec->gs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); + } else if (ilo_dev_gen(r->dev) == ILO_GEN(6) && vec->vs) { + count = ilo_shader_get_kernel_param(vec->vs, + ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT); + } else { + return; + } - skip = !session->binding_table_gs_changed; + r->state.gs.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder, + r->state.gs.SURFACE_STATE, count); break; case PIPE_SHADER_FRAGMENT: - surface_state = r->state.wm.SURFACE_STATE; - binding_table_state = &r->state.wm.BINDING_TABLE_STATE; - binding_table_state_size = &r->state.wm.BINDING_TABLE_STATE_size; + if (!session->binding_table_fs_changed) + return; + if (!vec->fs) + return; + + count = ilo_shader_get_kernel_param(vec->fs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); - skip = !session->binding_table_fs_changed; + r->state.wm.BINDING_TABLE_STATE = gen6_BINDING_TABLE_STATE(r->builder, + r->state.wm.SURFACE_STATE, count); break; default: - skip = true; break; } - - if (skip) - return; - - /* - * If we have seemingly less SURFACE_STATEs than before, it could be that - * we did not touch those reside at the tail in this upload. Loop over - * them to figure out the real number of SURFACE_STATEs. - */ - for (size = *binding_table_state_size; - size > session->num_surfaces[shader_type]; size--) { - if (surface_state[size - 1]) - break; - } - if (size < session->num_surfaces[shader_type]) - size = session->num_surfaces[shader_type]; - - *binding_table_state = gen6_BINDING_TABLE_STATE(r->builder, - surface_state, size); - *binding_table_state_size = size; } #undef DIRTY @@ -318,40 +311,26 @@ ilo_render_get_draw_surface_states_len(const struct ilo_render *render, switch (sh_type) { case PIPE_SHADER_VERTEX: - if (vec->view[sh_type].count) { - num_surfaces = ILO_VS_TEXTURE_SURFACE(vec->view[sh_type].count); - } else { - num_surfaces = ILO_VS_CONST_SURFACE( - util_last_bit(vec->cbuf[sh_type].enabled_mask)); - } - if (vec->vs) { - if (ilo_dev_gen(render->dev) == ILO_GEN(6)) { - const struct pipe_stream_output_info *so_info = - ilo_shader_get_kernel_so_info(vec->vs); + num_surfaces = ilo_shader_get_kernel_param(vec->vs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); - /* stream outputs */ - num_surfaces += so_info->num_outputs; + if (ilo_dev_gen(render->dev) == ILO_GEN(6)) { + num_surfaces += ilo_shader_get_kernel_param(vec->vs, + ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT); } } break; case PIPE_SHADER_GEOMETRY: - if (vec->gs && ilo_dev_gen(render->dev) == ILO_GEN(6)) { - const struct pipe_stream_output_info *so_info = - ilo_shader_get_kernel_so_info(vec->gs); - - /* stream outputs */ - num_surfaces += so_info->num_outputs; + if (vec->gs) { + num_surfaces = ilo_shader_get_kernel_param(vec->gs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); } break; case PIPE_SHADER_FRAGMENT: - if (vec->view[sh_type].count) { - num_surfaces = ILO_WM_TEXTURE_SURFACE(vec->view[sh_type].count); - } else if (vec->cbuf[sh_type].enabled_mask) { - num_surfaces = ILO_WM_CONST_SURFACE( - util_last_bit(vec->cbuf[sh_type].enabled_mask)); - } else { - num_surfaces = vec->fb.state.nr_cbufs; + if (vec->fs) { + num_surfaces = ilo_shader_get_kernel_param(vec->fs, + ILO_KERNEL_SURFACE_TOTAL_COUNT); } break; default: diff --git a/src/gallium/drivers/ilo/ilo_shader.c b/src/gallium/drivers/ilo/ilo_shader.c index fdbd2b88ea9..f4203aa9756 100644 --- a/src/gallium/drivers/ilo/ilo_shader.c +++ b/src/gallium/drivers/ilo/ilo_shader.c @@ -385,6 +385,14 @@ ilo_shader_info_parse_decl(struct ilo_shader_info *info, decl->Semantic.Name == TGSI_SEMANTIC_EDGEFLAG) info->edgeflag_out = decl->Range.First; break; + case TGSI_FILE_CONSTANT: + { + const int idx = (decl->Declaration.Dimension) ? + decl->Dim.Index2D : 0; + if (info->constant_buffer_count <= idx) + info->constant_buffer_count = idx + 1; + } + break; case TGSI_FILE_SYSTEM_VALUE: if (decl->Declaration.Semantic && decl->Semantic.Name == TGSI_SEMANTIC_INSTANCEID) @@ -1013,6 +1021,22 @@ ilo_shader_get_kernel_param(const struct ilo_shader_state *shader, val = kernel->pcb.cbuf0_size; break; + case ILO_KERNEL_SURFACE_TOTAL_COUNT: + val = kernel->bt.total_count; + break; + case ILO_KERNEL_SURFACE_TEX_BASE: + val = kernel->bt.tex_base; + break; + case ILO_KERNEL_SURFACE_TEX_COUNT: + val = kernel->bt.tex_count; + break; + case ILO_KERNEL_SURFACE_CONST_BASE: + val = kernel->bt.const_base; + break; + case ILO_KERNEL_SURFACE_CONST_COUNT: + val = kernel->bt.const_count; + break; + case ILO_KERNEL_VS_INPUT_INSTANCEID: val = shader->info.has_instanceid; break; @@ -1047,6 +1071,9 @@ ilo_shader_get_kernel_param(const struct ilo_shader_state *shader, case ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET: val = kernel->gs_offsets[2]; break; + case ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT: + val = kernel->gs_bt_so_count; + break; case ILO_KERNEL_GS_DISCARD_ADJACENCY: val = kernel->in.discard_adj; @@ -1054,6 +1081,12 @@ ilo_shader_get_kernel_param(const struct ilo_shader_state *shader, case ILO_KERNEL_GS_GEN6_SVBI_POST_INC: val = kernel->svbi_post_inc; break; + case ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE: + val = kernel->bt.gen6_so_base; + break; + case ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT: + val = kernel->bt.gen6_so_count; + break; case ILO_KERNEL_FS_INPUT_Z: case ILO_KERNEL_FS_INPUT_W: @@ -1071,6 +1104,12 @@ ilo_shader_get_kernel_param(const struct ilo_shader_state *shader, case ILO_KERNEL_FS_DISPATCH_16_OFFSET: val = 0; break; + case ILO_KERNEL_FS_SURFACE_RT_BASE: + val = kernel->bt.rt_base; + break; + case ILO_KERNEL_FS_SURFACE_RT_COUNT: + val = kernel->bt.rt_count; + break; default: assert(!"unknown kernel parameter"); diff --git a/src/gallium/drivers/ilo/ilo_shader.h b/src/gallium/drivers/ilo/ilo_shader.h index 77deee95ef0..c66513e27e0 100644 --- a/src/gallium/drivers/ilo/ilo_shader.h +++ b/src/gallium/drivers/ilo/ilo_shader.h @@ -38,6 +38,12 @@ enum ilo_kernel_param { ILO_KERNEL_SKIP_CBUF0_UPLOAD, ILO_KERNEL_PCB_CBUF0_SIZE, + ILO_KERNEL_SURFACE_TOTAL_COUNT, + ILO_KERNEL_SURFACE_TEX_BASE, + ILO_KERNEL_SURFACE_TEX_COUNT, + ILO_KERNEL_SURFACE_CONST_BASE, + ILO_KERNEL_SURFACE_CONST_COUNT, + ILO_KERNEL_VS_INPUT_INSTANCEID, ILO_KERNEL_VS_INPUT_VERTEXID, ILO_KERNEL_VS_INPUT_EDGEFLAG, @@ -47,9 +53,12 @@ enum ilo_kernel_param { ILO_KERNEL_VS_GEN6_SO_POINT_OFFSET, ILO_KERNEL_VS_GEN6_SO_LINE_OFFSET, ILO_KERNEL_VS_GEN6_SO_TRI_OFFSET, + ILO_KERNEL_VS_GEN6_SO_SURFACE_COUNT, ILO_KERNEL_GS_DISCARD_ADJACENCY, ILO_KERNEL_GS_GEN6_SVBI_POST_INC, + ILO_KERNEL_GS_GEN6_SURFACE_SO_BASE, + ILO_KERNEL_GS_GEN6_SURFACE_SO_COUNT, ILO_KERNEL_FS_INPUT_Z, ILO_KERNEL_FS_INPUT_W, @@ -57,6 +66,8 @@ enum ilo_kernel_param { ILO_KERNEL_FS_USE_KILL, ILO_KERNEL_FS_BARYCENTRIC_INTERPOLATIONS, ILO_KERNEL_FS_DISPATCH_16_OFFSET, + ILO_KERNEL_FS_SURFACE_RT_BASE, + ILO_KERNEL_FS_SURFACE_RT_COUNT, ILO_KERNEL_PARAM_COUNT, }; diff --git a/src/gallium/drivers/ilo/ilo_state.h b/src/gallium/drivers/ilo/ilo_state.h index c371716118c..a1d4b7bffcb 100644 --- a/src/gallium/drivers/ilo/ilo_state.h +++ b/src/gallium/drivers/ilo/ilo_state.h @@ -43,17 +43,7 @@ #define ILO_MAX_SO_BUFFERS 4 #define ILO_MAX_VIEWPORTS 1 -#define ILO_MAX_VS_SURFACES (ILO_MAX_CONST_BUFFERS + ILO_MAX_SAMPLER_VIEWS) -#define ILO_VS_CONST_SURFACE(i) (i) -#define ILO_VS_TEXTURE_SURFACE(i) (ILO_MAX_CONST_BUFFERS + i) - -#define ILO_MAX_GS_SURFACES (ILO_MAX_SO_BINDINGS) -#define ILO_GS_SO_SURFACE(i) (i) - -#define ILO_MAX_WM_SURFACES (ILO_MAX_DRAW_BUFFERS + ILO_MAX_CONST_BUFFERS + ILO_MAX_SAMPLER_VIEWS) -#define ILO_WM_DRAW_SURFACE(i) (i) -#define ILO_WM_CONST_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + i) -#define ILO_WM_TEXTURE_SURFACE(i) (ILO_MAX_DRAW_BUFFERS + ILO_MAX_CONST_BUFFERS + i) +#define ILO_MAX_SURFACES 256 /** * States that we track. diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c index fbf3216fa24..e41a1f64fcb 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_fs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_fs.c @@ -294,7 +294,7 @@ fs_lower_opcode_tgsi_indirect_const(struct fs_compile_context *fcc, simd_mode, GEN6_MSG_SAMPLER_LD, 0, - ILO_WM_CONST_SURFACE(dim)); + fcc->shader->bt.const_base + dim); tmp = tdst(TOY_FILE_VRF, tc_alloc_vrf(tc, param_size * 4), 0); inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); @@ -370,7 +370,7 @@ fs_lower_opcode_tgsi_const_gen6(struct fs_compile_context *fcc, msg_len = 1; desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false, - msg_type, msg_ctrl, ILO_WM_CONST_SURFACE(dim)); + msg_type, msg_ctrl, fcc->shader->bt.const_base + dim); tmp = tc_alloc_tmp(tc); @@ -417,7 +417,7 @@ fs_lower_opcode_tgsi_const_gen7(struct fs_compile_context *fcc, GEN6_MSG_SAMPLER_SIMD4X2, GEN6_MSG_SAMPLER_LD, 0, - ILO_WM_CONST_SURFACE(dim)); + fcc->shader->bt.const_base + dim); tmp = tc_alloc_tmp(tc); inst = tc_SEND(tc, tmp, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); @@ -714,10 +714,12 @@ fs_add_sampler_params_gen7(struct toy_compiler *tc, int msg_type, * Set up message registers and return the message descriptor for sampling. */ static struct toy_src -fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, +fs_prepare_tgsi_sampling(struct fs_compile_context *fcc, + const struct toy_inst *inst, int base_mrf, const uint32_t *saturate_coords, unsigned *ret_sampler_index) { + struct toy_compiler *tc = &fcc->tc; unsigned simd_mode, msg_type, msg_len, sampler_index, binding_table_index; struct toy_src coords[4], ddx[4], ddy[4], bias_or_lod, ref_or_si; int num_coords, ref_pos, num_derivs; @@ -976,7 +978,7 @@ fs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, assert(inst->src[sampler_src].file == TOY_FILE_IMM); sampler_index = inst->src[sampler_src].val32; - binding_table_index = ILO_WM_TEXTURE_SURFACE(sampler_index); + binding_table_index = fcc->shader->bt.tex_base + sampler_index; /* * From the Sandy Bridge PRM, volume 4 part 1, page 18: @@ -1100,7 +1102,7 @@ fs_lower_opcode_tgsi_sampling(struct fs_compile_context *fcc, int swizzles[4], i; bool need_filter; - desc = fs_prepare_tgsi_sampling(tc, inst, + desc = fs_prepare_tgsi_sampling(fcc, inst, fcc->first_free_mrf, fcc->variant->saturate_tex_coords, &sampler_index); @@ -1568,7 +1570,7 @@ fs_write_fb(struct fs_compile_context *fcc) mrf - fcc->first_free_mrf, 0, header_present, false, GEN6_MSG_DP_RT_WRITE, - ctrl, ILO_WM_DRAW_SURFACE(cbuf)); + ctrl, fcc->shader->bt.rt_base + cbuf); tc_add2(tc, TOY_OPCODE_FB_WRITE, tdst_null(), tsrc(TOY_FILE_MRF, fcc->first_free_mrf, 0), desc); @@ -1859,6 +1861,23 @@ fs_setup(struct fs_compile_context *fcc, fcc->shader->dispatch_16 = (fcc->dispatch_mode == GEN6_WM_DW5_16_PIXEL_DISPATCH); + fcc->shader->bt.rt_base = 0; + fcc->shader->bt.rt_count = fcc->variant->u.fs.num_cbufs; + /* to send EOT */ + if (!fcc->shader->bt.rt_count) + fcc->shader->bt.rt_count = 1; + + fcc->shader->bt.tex_base = fcc->shader->bt.rt_base + + fcc->shader->bt.rt_count; + fcc->shader->bt.tex_count = fcc->variant->num_sampler_views; + + fcc->shader->bt.const_base = fcc->shader->bt.tex_base + + fcc->shader->bt.tex_count; + fcc->shader->bt.const_count = state->info.constant_buffer_count; + + fcc->shader->bt.total_count = fcc->shader->bt.const_base + + fcc->shader->bt.const_count; + return true; } diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c index 2814662043a..aeeb1778375 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_gs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_gs.c @@ -488,7 +488,7 @@ gs_lower_opcode_emit_so_static(struct gs_compile_context *gcc) j == gcc->so_info->num_outputs - 1); - binding_table_index = ILO_GS_SO_SURFACE(j); + binding_table_index = gcc->shader->bt.gen6_so_base + j; gs_write_so(gcc, gcc->vars.tmp, index, out, write_commit, binding_table_index); @@ -1347,6 +1347,11 @@ gs_setup(struct gs_compile_context *gcc, gcc->first_free_mrf = 1; gcc->last_free_mrf = 15; + gcc->shader->bt.gen6_so_base = 0; + gcc->shader->bt.gen6_so_count = gcc->so_info->num_outputs; + + gcc->shader->bt.total_count = gcc->shader->bt.gen6_so_count; + return true; } @@ -1397,6 +1402,7 @@ append_gs_to_vs(struct ilo_shader *vs, struct ilo_shader *gs, int num_verts) vs->stream_output = true; vs->gs_offsets[num_verts - 1] = gs_offset; vs->gs_start_grf = gs->in.start_grf; + vs->gs_bt_so_count = gs->bt.gen6_so_count; ilo_shader_destroy_kernel(gs); diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_internal.h b/src/gallium/drivers/ilo/shader/ilo_shader_internal.h index 498e7433be7..98ec8dd0e04 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_internal.h +++ b/src/gallium/drivers/ilo/shader/ilo_shader_internal.h @@ -116,6 +116,7 @@ struct ilo_shader { /* for VS stream output / rasterizer discard */ int gs_offsets[3]; int gs_start_grf; + int gs_bt_so_count; void *kernel; int kernel_size; @@ -132,6 +133,17 @@ struct ilo_shader { int clip_state_size; } pcb; + /* binding table */ + struct { + int rt_base, rt_count; + int tex_base, tex_count; + int const_base, const_count; + + int gen6_so_base, gen6_so_count; + + int total_count; + } bt; + struct list_head list; /* managed by shader cache */ @@ -168,6 +180,8 @@ struct ilo_shader_info { uint32_t shadow_samplers; int num_samplers; + + int constant_buffer_count; }; /** diff --git a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c index da88e55f65a..a29baab10c1 100644 --- a/src/gallium/drivers/ilo/shader/ilo_shader_vs.c +++ b/src/gallium/drivers/ilo/shader/ilo_shader_vs.c @@ -130,7 +130,7 @@ vs_lower_opcode_tgsi_const_gen6(struct vs_compile_context *vcc, msg_len = 2; desc = tsrc_imm_mdesc_data_port(tc, false, msg_len, 1, true, false, - msg_type, msg_ctrl, ILO_VS_CONST_SURFACE(dim)); + msg_type, msg_ctrl, vcc->shader->bt.const_base + dim); tc_SEND(tc, dst, tsrc_from(header), desc, vcc->const_cache); } @@ -162,7 +162,7 @@ vs_lower_opcode_tgsi_const_gen7(struct vs_compile_context *vcc, GEN6_MSG_SAMPLER_SIMD4X2, GEN6_MSG_SAMPLER_LD, 0, - ILO_VS_CONST_SURFACE(dim)); + vcc->shader->bt.const_base + dim); tc_SEND(tc, dst, tsrc_from(offset), desc, GEN6_SFID_SAMPLER); } @@ -387,9 +387,11 @@ vs_add_sampler_params(struct toy_compiler *tc, int msg_type, int base_mrf, * Set up message registers and return the message descriptor for sampling. */ static struct toy_src -vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, +vs_prepare_tgsi_sampling(struct vs_compile_context *vcc, + const struct toy_inst *inst, int base_mrf, unsigned *ret_sampler_index) { + struct toy_compiler *tc = &vcc->tc; unsigned simd_mode, msg_type, msg_len, sampler_index, binding_table_index; struct toy_src coords, ddx, ddy, bias_or_lod, ref_or_si; int num_coords, ref_pos, num_derivs; @@ -502,7 +504,7 @@ vs_prepare_tgsi_sampling(struct toy_compiler *tc, const struct toy_inst *inst, assert(inst->src[sampler_src].file == TOY_FILE_IMM); sampler_index = inst->src[sampler_src].val32; - binding_table_index = ILO_VS_TEXTURE_SURFACE(sampler_index); + binding_table_index = vcc->shader->bt.tex_base + sampler_index; /* * From the Sandy Bridge PRM, volume 4 part 1, page 18: @@ -573,7 +575,7 @@ vs_lower_opcode_tgsi_sampling(struct vs_compile_context *vcc, unsigned swizzle_zero_mask, swizzle_one_mask, swizzle_normal_mask; bool need_filter; - desc = vs_prepare_tgsi_sampling(tc, inst, + desc = vs_prepare_tgsi_sampling(vcc, inst, vcc->first_free_mrf, &sampler_index); switch (inst->opcode) { @@ -1282,6 +1284,16 @@ vs_setup(struct vs_compile_context *vcc, vcc->shader->pcb.clip_state_size = vcc->variant->u.vs.num_ucps * (sizeof(float) * 4); + vcc->shader->bt.tex_base = 0; + vcc->shader->bt.tex_count = vcc->variant->num_sampler_views; + + vcc->shader->bt.const_base = vcc->shader->bt.tex_base + + vcc->shader->bt.tex_count; + vcc->shader->bt.const_count = state->info.constant_buffer_count; + + vcc->shader->bt.total_count = vcc->shader->bt.const_base + + vcc->shader->bt.const_count; + return true; } -- 2.30.2