From f358cca5a1800597d5309b6e1548e055744db21a Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 29 Jan 2017 17:14:05 +0100 Subject: [PATCH] Improve documentation --- docs/source/index.rst | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/docs/source/index.rst b/docs/source/index.rst index de64b96..9620eb3 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -7,16 +7,14 @@ hardware verification flows. SymbiYosys provides flows for the following formal tasks: * Bounded verification of safety properties (assertions) - * *Unbounded verification of safety properties* - * *Generation of test benches from cover statements* - * *Verification of liveness properties* - * *Formal equivalence checking* + * Unbounded verification of safety properties [TBD] + * Generation of test benches from cover statements [TBD] + * Verification of liveness properties [TBD] + * Formal equivalence checking [TBD] -(Italic items are features under construction and not available +(Items marked [TBD] are features under construction and not available at the moment.) -Contents: - .. toctree:: :maxdepth: 2 -- 2.30.2