From f363ff197e40d9eb560a3a9c1b0ec50ca9ccb5af Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 30 Apr 2022 06:53:23 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index 1e14c7748..493fb3f24 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -940,7 +940,8 @@ required.* Some operations in the Power ISA already target two 64-bit scalar registers: `lq` for example. Some mathematical algorithms are more -efficient when there are two outputs rather than one. 64-bit multiply +efficient when there are two outputs rather than one, providing +feedback loops between elements. 64-bit multiply for example actually internally produces a 128 bit result, which clearly cannot be stored in a single 64 bit register. Some ISAs recommend "macro op fusion": the practice of setting a convention whereby if @@ -950,8 +951,13 @@ selects the high part, then optimised micro-architectures may "fuse" those two instructions together, using Micro-coding techniques, internally. -Macro-op fusion would be perfect for Scalar Multiply Lo/Hi if it -was not for SVP64 Horizontal-First Loops. +The practice and convention of macro-op fusion however is not compatible +with SVP64 Horizontal-First, because Horizontal Mode may only +be applied to a single instruction at a time. Thus it becomes +necessary to add explicit more complex single instructions with +more operands than would normally be seen in another ISA. If it +was not for Power ISA already having LD/ST with update as well as +Condition Codes and `lq` this would be hard to justify. * [[isa/svfixedarith]] * [[isa/svfparith]] -- 2.30.2