From f3661310e4b61955223167b6f243e62cbca8d984 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 22 May 2021 11:59:32 +0000 Subject: [PATCH] correct PLL names --- .../full_core_4_4ksram_libresoc.v | 24 ++++----- .../full_core_4_4ksram_litex_ls180.v | 54 +++++++++---------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v index 18a9327..de16d04 100644 --- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -208761,7 +208761,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer" *) (* top = 1 *) (* generator = "nMigen" *) -module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_ana_o, pc_i); +module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i); (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) wire [1:0] \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) @@ -209125,9 +209125,9 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) output [63:0] pc_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1235" *) - output pll_18_o; + output pll_test_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *) - output pll_ana_o; + output pll_vco_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1251" *) wire pllclk_clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1251" *) @@ -209499,7 +209499,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) wire [1:0] wrappll_clk_sel_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *) - wire wrappll_pll_18_o; + wire wrappll_pll_test_o; assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) clk_sel_i; ti ti ( .TAP_bus__tck(TAP_bus__tck), @@ -209851,13 +209851,13 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t .clk_24_i(wrappll_clk_24_i), .clk_pll_o(wrappll_clk_pll_o), .clk_sel_i(wrappll_clk_sel_i), - .pll_18_o(wrappll_pll_18_o), - .pll_ana_o(pll_ana_o) + .pll_test_o(wrappll_pll_test_o), + .pll_vco_o(pll_vco_o) ); assign ti_coresync_clk = wrappll_clk_pll_o; assign pllclk_rst = rst; assign wrappll_clk_sel_i = \$1 ; - assign pll_18_o = wrappll_pll_18_o; + assign pll_test_o = wrappll_pll_test_o; assign wrappll_clk_24_i = clk; assign pllclk_clk = wrappll_clk_pll_o; endmodule @@ -216829,7 +216829,7 @@ endmodule (* \nmigen.hierarchy = "test_issuer.wrappll" *) (* generator = "nMigen" *) -module wrappll(clk_24_i, pll_18_o, clk_sel_i, pll_ana_o, clk_pll_o); +module wrappll(clk_24_i, pll_test_o, clk_sel_i, pll_vco_o, clk_pll_o); (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) input clk_24_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *) @@ -216837,16 +216837,16 @@ module wrappll(clk_24_i, pll_18_o, clk_sel_i, pll_ana_o, clk_pll_o); (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *) input [1:0] clk_sel_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *) - output pll_18_o; + output pll_test_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *) - output pll_ana_o; + output pll_vco_o; pll pll ( .a0(clk_sel_i[0]), .a1(clk_sel_i[1]), - .div_out_test(pll_18_o), + .div_out_test(pll_test_o), .out(clk_pll_o), .\ref (clk_24_i), - .vco_test_ana(pll_ana_o) + .vco_test_ana(pll_vco_o) ); endmodule diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 28d409c..25561dd 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,16 +1,16 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:44:09 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 12:58:35 //-------------------------------------------------------------------------------- module ls180( - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, + input wire uart_tx, + input wire uart_rx, input wire [15:0] gpio_i, output wire [15:0] gpio_o, output wire [15:0] gpio_oe, - input wire uart_tx, - input wire uart_rx, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -23,13 +23,13 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, input wire eint_0, input wire eint_1, input wire eint_2, - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -156,18 +156,18 @@ reg [63:0] libresocsim_libresoc0 = 64'd0; wire libresocsim_libresoc1; wire libresocsim_libresoc2; wire [63:0] libresocsim_libresoc3; -wire libresocsim_libresoc_pll_18_o; +wire libresocsim_libresoc_pll_vco_o; wire [1:0] libresocsim_libresoc_clk_sel; -wire libresocsim_libresoc_pll_ana_o; -reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire libresocsim_libresoc_constraintmanager_spimaster_miso; +wire libresocsim_libresoc_pll_test_o; +wire libresocsim_libresoc_constraintmanager_i2c_scl; +wire libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; -reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -180,13 +180,13 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire libresocsim_libresoc_constraintmanager_spimaster_miso; wire libresocsim_libresoc_constraintmanager_eint_0; wire libresocsim_libresoc_constraintmanager_eint_1; wire libresocsim_libresoc_constraintmanager_eint_2; -wire libresocsim_libresoc_constraintmanager_i2c_scl; -wire libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -1581,8 +1581,8 @@ wire sdrio_clk_118; assign libresocsim_libresoc_reset = libresocsim_reset; assign libresocsim_libresoc_clk_sel = sys_clksel_i; -assign sys_pll_testout_o = libresocsim_libresoc_pll_18_o; -assign sys_pll_vco_o = libresocsim_libresoc_pll_ana_o; +assign sys_pll_testout_o = libresocsim_libresoc_pll_test_o; +assign sys_pll_vco_o = libresocsim_libresoc_pll_vco_o; always @(*) begin eint_tmp <= 3'd0; eint_tmp[0] <= libresocsim_libresoc_constraintmanager_eint_0; @@ -6084,8 +6084,8 @@ test_issuer test_issuer( .mtwi_sda__pad__o(i2c_sda_o), .mtwi_sda__pad__oe(i2c_sda_oe), .pc_o(libresocsim_libresoc3), - .pll_18_o(libresocsim_libresoc_pll_18_o), - .pll_testout_o(libresocsim_libresoc_pll_ana_o), + .pll_test_o(libresocsim_libresoc_pll_test_o), + .pll_vco_o(libresocsim_libresoc_pll_vco_o), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), -- 2.30.2