From f390aac8bf2fc360589ec48e1d77c1afadadbf0d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 11 Mar 2020 18:16:35 +0000 Subject: [PATCH] enable rvfi, fix imports --- src/soc/minerva/core.py | 2 +- src/soc/minerva/units/rvficon.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/minerva/core.py b/src/soc/minerva/core.py index c73d5fd0..51e94e6d 100644 --- a/src/soc/minerva/core.py +++ b/src/soc/minerva/core.py @@ -14,7 +14,7 @@ from soc.minerva.units.decoder import InstructionDecoder from soc.minerva.units.divider import Divider, DummyDivider from soc.minerva.units.exception import ExceptionUnit from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit, PCSelector -from soc.minerva.units.rvficon import RVFIController +from soc.minerva.units.rvficon import RVFIController, rvfi_layout from soc.minerva.units.loadstore import (BareLoadStoreUnit, CachedLoadStoreUnit, DataSelector) from soc.minerva.units.logic import LogicUnit diff --git a/src/soc/minerva/units/rvficon.py b/src/soc/minerva/units/rvficon.py index 266fd12a..a167f496 100644 --- a/src/soc/minerva/units/rvficon.py +++ b/src/soc/minerva/units/rvficon.py @@ -1,7 +1,7 @@ from functools import reduce from operator import or_ -from nmigen import Elaboratable, Module, Signal, Record +from nmigen import Elaboratable, Module, Signal, Record, Const from nmigen.hdl.rec import DIR_FANOUT from ..wishbone import wishbone_layout -- 2.30.2