From f3957586e210d6d7c7c40b8b4080107c28c1c744 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 8 Jun 2020 23:19:24 +0200 Subject: [PATCH] [breaking-change] nexys4ddr: fix UART RTS/CTS pins. According to the schematic, RTS is E5 and CTS is D3. Previously these were reversed to work around signal direction set in UARTResource. Un-reverse the signals, and set correct direction by passing role=dce. Ref. https://reference.digilentinc.com/_media/nexys4-ddr:nexys_4_ddr_sch.pdf --- nmigen_boards/nexys4ddr.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nmigen_boards/nexys4ddr.py b/nmigen_boards/nexys4ddr.py index 02dc101..f67979c 100644 --- a/nmigen_boards/nexys4ddr.py +++ b/nmigen_boards/nexys4ddr.py @@ -100,8 +100,9 @@ class Nexys4DDRPlatform(Xilinx7SeriesPlatform): Attrs(IOSTANDARD="LVCMOS33")), UARTResource(0, - rx="C4", tx="D4", rts="D3", cts="E5", - attrs=Attrs(IOSTANDARD="LVCMOS33")), + rx="C4", tx="D4", rts="E5", cts="D3", + attrs=Attrs(IOSTANDARD="LVCMOS33"), + role="dce"), Resource("ps2_host", 0, Subsignal("clk", Pins("F4", dir="i")), -- 2.30.2