From f39a25989b0f01f4f4a58755522a9cf147f0c02a Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 15 Jun 2022 00:58:42 +0100 Subject: [PATCH] --- openpower/sv/svp64_quirks.mdwn | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn index 85ffc48cb..b01d2964e 100644 --- a/openpower/sv/svp64_quirks.mdwn +++ b/openpower/sv/svp64_quirks.mdwn @@ -238,7 +238,16 @@ the hardware know what the remainder of the Prefix bits mean: how they are formatted, even without having to examine the Suffix to which they are applied. -SVP64 has such pressure on its 24 +SVP64 has such pressure on its 24-bit encoding that it was simply +not possible to perform the same trick used by Power ISA 3.1 Prefixing. +Therefore, rather unfortunately, it becomes necessary to perform +a *partial decoding* of the v3.0 Suffix before the 24-bit SVP64 RM +Fields may be identified. Fortunately this is straightforward, and +does not rely on any outside state, and even more fortunately +for a Multi-Issue Execution decoder, the length 32/64 is also +easy to identify by looking for the EXT001 pattern. Once identified +the 32/64 bits may be passed independently to multiple Decoders in +parallel. # Single Predication -- 2.30.2