From f3ae22f488119aa273882adcd6537bc6b54dc66a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 1 Apr 2012 16:39:11 +0200 Subject: [PATCH] fhdl/verilog: initialize internal read-only signals with their reset values --- migen/fhdl/verilog.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 854da372..f6326e74 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -220,6 +220,16 @@ def _printmemories(f, ns, handler, clk): r += handler(memory, ns, clk) return r +def _printinit(f, exclude, ns): + r = "" + signals = list_signals(f) - exclude - list_targets(f) + if signals: + r += "initial begin\n" + for s in signals: + r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset) + ";\n" + r += "end\n\n" + return r + def convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, return_ns=False, @@ -243,6 +253,7 @@ def convert(f, ios=set(), name="top", r += _printsync(f, ns, clk_signal, rst_signal) r += _printinstances(f, ns, clk_signal, rst_signal) r += _printmemories(f, ns, memory_handler, clk_signal) + r += _printinit(f, ios, ns) r += "endmodule\n" if return_ns: -- 2.30.2