From f3cdd466109eb4cf13cc6b89ea307857d26dff00 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 2 Oct 2022 15:13:04 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index a51e4c387..266924467 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -26,10 +26,10 @@ Dynamic SIMD ALUs for maximum performance and effectiveness. # Analysis Covered in [[biginteger/analysis]] the summary is that standard `adde` -is sufficient for SVP64 Vectorisation of big-integer addition (and subfe +is sufficient for SVP64 Vectorisation of big-integer addition (and `subfe` for subtraction) but that big-integer shift, multiply and divide require an -extra 3-in 2-out instructions, similar to Intel's `mulx` and -`idiv`, to be efficient. +extra 3-in 2-out instructions, similar to Intel's `shld`, `shrd`, +`mulx` and `idiv`, to be efficient. The same instruction (`maddedu`) is used for both because 'maddedu''s primary purpose is to perform a fused 64-bit scalar multiply with a large vector, where that result is Big-Added for Big-Multiply, but Big-Subtracted for -- 2.30.2